155
Bit 9—Interrupt Vector Mode Select (VECMD): This bit selects whether to set the IRQ/IRL
interrupt vector number according to the auto-vector mode or the external vector mode. In auto-
vector mode, the internally determined vector number is set. In external vector mode, a value
between 0 and 127 can be input as the vector number from the external vector number input pins
(D7–D0).
Bit 9: VECMD
Description
0
Auto vector mode, set internally (initial value)
1
External vector mode, external input
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
Description
0
Interrupt request is detected on falling edge of NMI input (initial value)
1
Interrupt request is detected on rising edge of NMI input
Bits 7–4—Reserved: These bits always read 0. The write value should always be 0.
Bits 3-0—IRQ0–IRQ3 Sense Select (IRQ0S-IRQ3S): IRQ0S–IRQ3S select whether the falling
edge or low level of the IRQ inputs is sensed at the pins IRQ0–IRQ3, respectively, when the mode
is IRQ mode (EXIMD = 0).
Bits 3–0: IRQ0S–IRQ3S
Description
0
Interrupt is requested when IRQ input is low (initial value)
1
Interrupt is requested on falling edge of IRQ input
5.4
Interrupt Operation
5.4.1
Interrupt Sequence
The sequence of interrupt operations (figure 5.5) is explained below:
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt of the interrupt requests sent,
following the priorities set in interrupt priority registers A, B, C, and D (IPRA, IPRB, IPRC,
and IPRD). Lower-priority interrupts are held pending. If two of these interrupts have the same
priority level or if multiple interrupts occur within a single module, the interrupt with the
highest default priority or the highest priority within its IPR setting unit (as indicated in tables
5.4, 5.5, and 5.6) is selected.