148
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priorities between 0 and 15 can be assigned
to individual on-chip peripheral modules in interrupt priority registers B, C, and D (IPRB, IPRC,
and IPRD). On-chip peripheral module interrupt exception processing sets the interrupt mask level
bits (I3–I0) in SR to the priority-level value of the on-chip peripheral module interrupt that was
accepted.
5.2.6
Interrupt Exception Vectors and Priority
Tables 5.4, 5.5, and 5.6 list interrupt sources and their vector numbers, vector table address offsets
and interrupt priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the address offsets. During interrupt exception processing, the
exception service routine start address indicated by the vector table address is fetched from the
vector table. See table 4.6, Calculating Exception Processing Vector Table Addresses, for more
information on this calculation.
When the processor is in the IRQ mode, interrupt priorities 0–15 can be assigned to the IRQ
interrupts using interrupt priority register A (IPRA). When the processor is in IRL mode, IRL
interrupts IRL15–IRL1 have interrupt priorities of 15–1, respectively vector numbers for the IRQ
or IRL interrupts can be the auto-vector numbers shown in tables 5.4 and 5.5, or an external vector
number from 0–127.
On-chip peripheral module interrupts can be freely assigned a priority level between 0 and 15 for
each module by configuring the interrupt priority registers B, C, and D (IPRB, IPRC, and IPRD).
The Priority within IPR Setting Unit column of table 5.6 indicates the relative priority for interrupt
sources that share the same IPR field; this priority-level order cannot be changed. A reset assigns
priority 0 to on-chip peripheral module interrupts. If the same priority is assigned to two or more
interrupt sources and interrupts from those sources occur simultaneously, their priorities are the
default priorities indicated at the right in tables 5.4, 5.5, and 5.6.