![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_21.png)
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Figure 14.21 FRT Input/Output Timing (CKE:CKP = 1:1)......................................................... 461
Figure 14.22 FRT Clock Input Timing (CKE:CKP = 1:1) .......................................................... 461
Figure 14.23 FRT Clock Input Timing (CKE:CKP = 1:1) .......................................................... 462
Figure 14.24 SCI Clock Input/Output Timing ............................................................................. 462
Figure 14.25 SCI Input/Output Timing (Clock Synchronization Mode) ..................................... 462
Figure 14.26 SIO Input Clock Timing ......................................................................................... 463
Figure 14.27 SIO Receive Timing ............................................................................................... 463
Figure 14.28 SIO Send Timing (TMn = 0 Mode)........................................................................ 463
Figure 14.29 SIO Send Timing (TMn = 1 Mode) ....................................................................... 464
Figure 14.30 H-UDI Clock Timing.............................................................................................. 464
Figure 14.31 H-UDI
TRST Timing ............................................................................................. 464
Figure 14.32 H-UDI Input/Output Timing................................................................................... 465
Figure 14.33
DREQ0, DREQ1 Input Timing (1)......................................................................... 465
Figure 14.34
DREQ0, DREQ1 Input Timing (2)......................................................................... 466
Figure 14.35 I/O Port Input/Output Timing (CKE:CKP = 1:1) ................................................... 466
Figure 14.36 I/O Port Input/Output Timing (CKE:CKP = 1:1) ................................................... 466
Figure 14.37 Interrupt Vector Fetch Cycle (No Waits)................................................................ 467
Figure 14.38 Interrupt Vector Fetch Cycle (1 Wait).................................................................... 468
Figure 14.39 Bus Arbitration Cycle ............................................................................................. 469
Figure 14.40 DMA Single-Address Transfer Timing (Read Wait, DRAM)................................ 470
Figure 14.41 DMA Single-Address Transfer Timing (Write Wait, DRAM) .............................. 471
Figure 14.42 NMI Pulse Width.................................................................................................... 472
Figure 14.43 Output Load Circuit................................................................................................ 473
Figure C.1
Memory map for ordering ROM ............................................................................ 487
Figure F.1
External Dimensions............................................................................................... 491
Tables
Table 1.1
Pin Configuration....................................................................................................
7
Table 1.2
BSC Memory Interfaces..........................................................................................
21
Table 1.3
Power-Down Modes ...............................................................................................
28
Table 2.1
SR Register Bits......................................................................................................
33
Table 2.2
DSR Register Bits ...................................................................................................
37
Table 2.3
Initial Values of Registers ......................................................................................
38
Table 2.4
Source Register Data Formats for DSP Instructions ..............................................
44
Table 2.5
Destination Register Data Formats for DSP Instructions .......................................
45
Table 2.6
Sign Extension of Word Data .................................................................................
46
Table 2.7
Delayed Branch Instructions...................................................................................
47
Table 2.8
T Bit ........................................................................................................................
47
Table 2.9
Immediate Data Accessing .....................................................................................
48
Table 2.10
Absolute Address Accessing ..................................................................................
48
Table 2.11
Displacement Accessing .........................................................................................
49
Table 2.12
CPU Instruction Addressing Modes and Effective Addresses................................
50
Table 2.13
Overview of Data Transfer Instructions .................................................................
54