292
Bit 0—DMA Master Enable (DME): DME enables or disables the DMA transfers on all channels.
An individual channel is enabled for a DMA transfer when the DE bit in the corresponding
DCHCR and the DME bit of DMAOR are both set to 1. For this to be effective, however, the TE
bit of the corresponding DCHCR and the NMIF and AE bits of DMAOR must also be cleared to
0. When the DME bit is cleared, DMA transfers on all channels are aborted.
Bit 0: DME
Description
0
Disable DMA transfers on all channels (initial value)
1
Enable DMA transfers on all channels
8.3
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the specified
channel priorities; when the transfer end conditions are satisfied, it ends the transfer. Transfers can
be requested in three modes: auto-request, external request, and on-chip module request. Transfer
can be in either single-address mode or dual-address mode. The bus mode can be either burst or
cycle-steal.
8.3.1
DMA Transfer Flow
After the DMA source address registers (DSAR), DMA destination address registers (DAR),
DMA transfer count registers (DTCR), DMA channel control registers (DCHCR), and DMA
operation register (DMAOR) are loaded with the desired values, the DMAC transfers data
according to the following procedure:
1. Verifies that the transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
2. When the DMAC receives a transfer request and the transfer is enabled, the DMAC transfers
one unit of data. (For an auto-request, the transfer begins automatically when the DE bit and
DME bit are set to 1. The DTCR value will be decremented by 1). The actual transfer flows
vary by address mode and bus mode.
3. When the specified number of transfers have been completed (for example, DTCR reaches 0),
the transfer ends normally. If the IE bit of the DCHCR is set to 1 at this time, a DEI interrupt
request is sent to the CPU.
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
aborted. Transfers are also aborted when the DE bit of DCHCR or the DME bit of DMAOR is
changed from 1 to 0.
Figure 8.2 is a flowchart of this procedure.