![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_167.png)
144
5.2.1
NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by
edge. The NMI edge select bit (NMIE) in the interrupt control register (ICR) selects either the
rising or falling edge (see section 5.3.2, Interrupt Control Register). NMI interrupt exception
processing sets the interrupt mask level bits (I3–I0) in the status register (SR) to level 15.
5.2.2
User Break Interrupt
A user break interrupt has priority 15. It occurs when the break condition set in the user break
controller (UBC) is satisfied. User break interrupt exception processing sets the interrupt mask
level bits (I3–I0) in SR to level 15. For more information about the user break interrupt, see
Section 6, User Break Controller.
5.2.3
H-UDI Interrupt
A Hitachi user debug interface (H-UDI) interrupt has priority 15. It occurs when there is a serial
input of an H-UDI interrupt instruction. The H-UDI interrupt exception processing sets the
interrupt mask level bits (I3–I0) in the SR to level 15. For more information about the H-UDI
interrupt, see Section 13, H-UDI.
5.2.4
External Interrupts
The SH7410 processor has two external interrupt modes: IRQ mode and IRL mode. In IRQ mode,
the four external signals are individual interrupt sources (IRQ3–IRQ0). Each interrupt source has
an interrupt vector and can select priorities. In IRL mode, the four external interrupt signals
specify the priorities, from 1 to 15. The external interrupt mode bit (EXIMD) in the ICR specifies
which of these two modes is used (see section 5.3.2, Interrupt Control Register).
IRQ Interrupt Mode: Each IRQ interrupt corresponds to an input on one of the IRQ0–IRQ3 pins.
IRQ sense select bits 3–0 (IRQ0S–IRQ3S) in the interrupt control register (ICR) can select low-
level sensing or falling-edge sensing for each pin independently. Interrupt priority register A
(IPRA) can select priorities from 0–15 for each pin independently. IRQ interrupt exception
processing sets the interrupt mask level bits (I3–I0) in SR to the priority value of the IRQ interrupt
that was accepted. Set the interrupt vector mode select bit (VECMD) in ICR to enable external
input of the vector numbers. An external vector number is a value from 0 to 127 input on the
external vector input pins (D7–D0) during an interrupt vector fetch bus cycle. Internal vectors are
called auto vectors and externally input vectors are called external vectors.
When an IRQ interrupt is accepted in external vector mode, the IRQ interrupt priority is output
from the interrupt acceptance level output signals (A3–A0). The external vector fetch signal
(
IVECF) is also asserted. The external vector number is read from signals D7–D0 at this time.
Figures 5.2 and 5.3 show interrupt connection examples.