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Table 4.11
Exceptions Triggered by Instructions
Type
Source Instruction
Comment
Trap instructions
TRAPA
—
Illegal slot
instructions
Undefined code* or an instruction
that rewrites the PC placed
immediately after a delay branch
instruction (as in the delay slot)
Delay branch instructions: JMP, JSR, BRA,
BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
General illegal
instructions
Undefined code* anywhere
besides in a delay slot
—
Note:
No general illegal instruction or illegal slot instruction exception processing is executed for
DSP instruction format (double data transfer instruction, single data transfer instruction,
parallel processing instruction) undefined codes.
4.5.2
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing begins. The CPU
operates as follows:
1. The status register (SR) is saved on the stack.
2. The program counter (PC) is saved on the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The exception service routine start address is fetched from the exception processing vector
table entry that corresponds to the vector number specified in the TRAPA instruction.
Execution begins from that address. The jump that occurs is not a delay branch.
4.5.3
Illegal Slot Instructions
An instruction placed immediately after a delay branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, illegal slot exception
processing begins when the undefined code is decoded. When an instruction that rewrites the
program counter (PC) is placed in a delay slot, illegal slot exception processing starts when the
instruction that rewrites the PC is decoded. No general illegal instruction or illegal slot instruction
exception processing is executed for DSP instruction format (double data transfer instruction,
single data transfer instruction, parallel processing instruction) undefined codes. The CPU handles
an illegal slot instruction as follows:
1. The status register (SR) is saved on the stack.
2. The program counter (PC) is saved on the stack. The PC value saved is the jump address of the
delay branch instruction immediately before the undefined code or the instruction that rewrites
the PC.