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Section 6 User Break Controller (UBC)
6.1
Overview
The user break controller (UBC) provides functions that simplify program debugging. Break
conditions are set in the UBC and a user break interrupt is generated according to the conditions of
the bus cycle generated by the CPU or on-chip DMAC.
These functions make it easy to design an effective self-monitoring debugger, enabling the
debugging of programs without using an in-circuit emulator.
The UBC has the following features:
Issues a user break interrupt when break conditions are satisfied.
Two break channels (channels A and B). User break interrupts can be requested from channels
A and B independently or sequentially. For a sequential break setting, a break interrupt is
issued when a match of the channel B break condition occurs after the channel A break
condition has been matched.
The CPU and DMAC can read and write the UBC registers. The following break compare
conditions can be set in the UBC:
Address (bit mask enabled): On channel A, specifies an address for the break condition on
the internal address bus (IAB). On channel B, specifies an address on the IAB or the X-
memory address bus (XAB)/Y-memory address bus (YAB).
Data (only on channel B, bit mask enabled): Any one of the three data buses (internal data
bus (IDB), X-memory data bus (XDB) or Y-memory data bus (YDB)) can be selected.
Bus master: CPU or DMAC
Bus cycle: Instruction fetch or data access
Read or write
Operand size: Byte, word, or longword
Able to specify in an instruction fetch cycle that a break is set before or after an instruction is
executed.
Can specify the number of repeat times as a break condition (only for channel B), up to a
maximum of 212 – 1 times.
PC trace keeps four pairs of branch source and branch destination addresses.
In certain circumstances, some exception types, including user breaks generated by the UBC, are
not immediately accepted. See section 4.6, When Exception Sources Are Not Accepted.
Figure 6.1 shows a block diagram of the UBC.