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On-chip ROM and RAM are accessed in one cycle
Fast peripheral modules, such as the UBC, are accessed in one CPU clock cycle
Intermediate-speed peripheral modules (SIO) are accessed in two peripheral module clock
cycles
Slow peripheral modules, such as FRT and SCI, are accessed in three peripheral module
clock cycles
External address space
Divided into four separate areas called CS0 through CS3
A maximum linear 16 Mbytes for each of the external address areas
The type of memory connected can be separately specified for each space (SRAM, DRAM,
pseudo-SRAM, burst ROM, etc.)
Bus width can be separately selected for each area (8, 16, or 32 bits)
Wait state insertion can be controlled by software (using bit settings) and hardware (using
the external
WAIT signal)
Outputs control signals with the proper timing for each area
Refresh
Supports CAS-before-RAS refresh (auto-refresh for pseudo-SRAM) and self-refresh
The refresh interval can be set using the refresh counter and a clock select
The refresh controller can be used as an interval timer, generating a CMI interrupt request
when the value of the RTCNT register is equal to the value of the RTCOR register (this
usually indicates a refresh cycle request)
Ordinary space interface (for SRAM, ROM, and memory-mapped external devices)
Waits specified by software (register setting) or hardware (WAIT signal)
DRAM interface
Multiplexes the row and column address outputs
Supports two-CAS 16-bit data width DRAM
Supports fast-page mode and EDO burst operation
Includes a precharge step to ensure RAS precharge time
Waits specified by software (register setting)
Supports RAS-down mode, which maintains the assertion of the RAS signal between burst
accesses
Supports CAS-before-RAS refresh and self-refresh
Pseudo-SRAM interface
Waits specified by software (register setting)
Supports static-column access
Supports auto-refresh and self-refresh
Burst ROM interface
Has the features of the ordinary space interface, but includes a burst mode