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1.8.1
Program Execution State
In the program execution state, the processor sequentially executes program instructions.
1.8.2
Exception Processing State
The exception processing state is a transient state that occurs when the processor's normal
execution flow is altered by an exception source, such as a reset or an interrupt.
For a reset, the initial values of the program counter (PC) and the stack pointer (SP) are fetched
from the exception-processing vector table and stored. The processor then branches to the
execution start address and begins execution of the program.
For any other type of exception, the processor saves the PC and the contents of the status register
(SR) to the stack. The processor loads the start address of the exception-processing routine from
the exception-processing vector table; the processor then branches to that address and the program
starts executing, thereby entering the program execution state.
Section 4 describes exception processing.
1.8.3
Reset State
The processor enters the reset state when the
RST signal on the external bus is asserted. If the
NMI signal on the external bus is high when
RST is asserted, a power-on reset occurs; if NMI is
low, a manual reset occurs.
During a power-on reset, the processor initializes all of its internal registers, including the on-chip
peripheral module registers. During a manual reset, the processor also initializes all of its registers,
with the exception of those in the bus-state controller, the user-break controller, the system
controller, and the pin-function controller. The BSC is not initialized during manual reset so that
the refresh of DRAM can continue.
1.8.4
Power-Down State
In the power-down state, the CPU operation halts and power consumption declines. The SLEEP
instruction places the processor in the power-down state. This state has two modes: sleep mode
and standby mode. The processor also has a module standby function. Table 1.3 summarizes the
power-down modes.
Sleep Mode: When the standby bit SBY in the standby control register SBYCR is cleared to 0 and
a SLEEP instruction is executed, the processor transitions from the program execution state to
sleep mode. In sleep mode, the CPU halts while maintaining the contents of its internal registers
and the data in its on-chip RAM. The on-chip peripheral modules do not halt in the sleep mode. A