
330
8.4
Examples
8.4.1
Transfer between On-Chip SCI and External Memory
Table 8.7 shows the transfer conditions and register settings to transfer receive data of the on-chip
serial communication interface (SCI) channel 0 to external memory using DMAC channel 3.
Table 8.7
Transfer between On-Chip SCI and External Memory
Transfer Conditions
Register
Setting
Transfer source: SCRDR0 of on-chip SCI0
DSAR3
H'0D000105
Transfer destination: external memory area CS1
DAR3
H'01000000
Number of transfers: 64
DTCR3
H'0040
Transfer destination address: incremented
DCHCR3
H'4405
Transfer source address: fixed
Transfer request source (transfer request signal): SCI0 (RXI0)
Bus mode: cycle steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer
Channel priorities: fixed (ch0 > ch3 > ch2 > ch1) (all channels
transfer enabled)
DMAOR
H'0001
8.4.2
Cautions
1. Before rewriting the DCHCR, first clear the DE bit of the specified channel or the DME bit of
the DMAOR to 0.
2. The DMAOR’s NMIF bit will be set if an NMI interrupt is input, even if the DMAC is not
running.
3. Change to standby mode only after the DMAOR’s DME bit is set to 0.
4. Do not access the DMAC, BSC, or SYSC on-chip peripheral modules with the DMAC.
5. Do not change to standby mode or module standby mode during a DMA transfer.
6. When the DMAC is transferring data from outside to inside the chip due to an external request,
clear the AM bit of the DMA channel control register (DCHCR) to 0. When transferring from
within the chip to outside, set this bit to 1.
7. When performing DMA transfers due to DMA transfer request signals from peripheral
modules, there are some cases where the following DMA transfers will become impossible if
the DMA transfer request signal from the peripheral module is not cleared in time for the next
transfer request signal output from that module.