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Figure 8.36
DREQ Sampling Timing (Burst, Dual-Address, DREQ Level Detection
CKM:CLK = 4:1).................................................................................................... 321
Figure 8.37
DREQ Sampling Timing (Burst, Dual-Address, DREQ Level Detection
CKM:CLK = 1:1).................................................................................................... 322
Figure 8.38
DREQ Sampling Timing (Burst, Dual-Address, DREQ Level Detection
CKM:CLK = 2:1).................................................................................................... 323
Figure 8.39
DREQ Sampling Timing (Burst, Dual-Address, DREQ Level Detection
CKM:CLK = 4:1).................................................................................................... 324
Figure 8.40 Example of
DREQ Sampling Timing when a DMA Transfer Request Occurs
for a Channel with Higher Priority than the Executing Channel............................ 326
Figure 8.41 Example of
DREQ Sampling Timing in EDO RAS-Down Mode, for DMAC
Burst Mode, Single-Address Transfer (Device
→ Memory), and DREQ Level
Request (Case Where RAS Precharge, RAS-CAS Delay, and CAS Assert Interval
Waits are All 0)....................................................................................................... 328
Figure 9.1
FRT Block Diagram................................................................................................ 332
Figure 9.2
FRC Access Operation (CPU to FRC (H'AA55) Write) ........................................ 341
Figure 9.3
FRC Access Operation (FRC to CPU (H'AA55) Read) ......................................... 342
Figure 9.4
Count Timing (Internal Clock Operation) .............................................................. 343
Figure 9.5
Count Timing (External Clock Operation) ............................................................. 343
Figure 9.6
Output Timing for Output Compare A ................................................................... 344
Figure 9.7
Compare Match A Clear Timing ............................................................................ 344
Figure 9.8
Input Capture Signal Timing (Normal) .................................................................. 345
Figure 9.9
Input Capture Signal Timing (When Input Capture Input is Input During an
FICR Read) ............................................................................................................. 345
Figure 9.10 ICF Setting Timing ................................................................................................. 346
Figure 9.11 OCF Setting Timing................................................................................................ 346
Figure 9.12 OVF Setting Timing ............................................................................................... 347
Figure 9.13 Pulse Output Example ............................................................................................ 349
Figure 9.14 Contention between FRC Write and Clear ............................................................. 350
Figure 9.15 Contention between FRC Write and Increment...................................................... 351
Figure 9.16 Contention between FOCR and Compare Match ................................................... 352
Figure 9.17 Internal Clock Switching and FRC Operation Timing ........................................... 353
Figure 10.1 SCI Block Diagram................................................................................................. 356
Figure 10.2 Data Format in Asynchronous Mode (8-Bit Data, with Parity, Two Stop Bits) .... 373
Figure 10.3 Output Clock and Communication Data Phase Relationship
(Asynchronous Mode) ............................................................................................ 374
Figure 10.4 SCI Initialization Flowchart.................................................................................... 375
Figure 10.5 Serial Transmission Flowchart ............................................................................... 376
Figure 10.6 Transmit Operation in Asynchronous Mode Example (8-Bit Data, with Parity,
One Stop Bit) .......................................................................................................... 378
Figure 10.7 Receiving Serial Data Flowchart ............................................................................ 379
Figure 10.8 SCI Receive Operation with Framing Error Example (8-Bit Data, with Parity,
One Stop Bit) .......................................................................................................... 381