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8.3.6
DMA Transfer End Conditions
The DMA transfer end conditions depend on whether the transfer for an individual channel
terminates or the transfers in all channels terminate together.
Individual Channel End Conditions: There are two termination conditions. A transfer ends
when the value of the channel’s DMA transfer count register (DTCR) is 0, or when the DE bit of
the channel’s DCHCR is cleared to 0.
When DTCR is 0: When the DTCR value becomes 0 and the DMA transfer ends, the transfer
end flag bit (TE) is set in DCHCR. If the IE (interrupt enable) bit is set, a DMAC interrupt
(DEI) request is sent to the CPU.
When DE of DCHCR is 0: When the DE bit in DCHCR is cleared, the DMA transfer on the
given channel is aborted. The TE bit is not set when this happens.
Conditions for Simultaneous End of All Channels: Transfers on all channels end when either
the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME
bit in DMAOR is cleared to 0.
Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or a
DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR, and all channels stop
their transfers. DSAR, DAR, and DTCR are all updated by the transfer immediately preceding
the halt. The TE bit is not set. To resume the transfers following NMI interrupt exception
processing or address error exception processing, clear the appropriate flag bit to 0. When a
channel’s DE bit is then set to 1, the transfer on that channel will restart. To avoid restarting a
transfer on a particular channel, keep its DE bit cleared to 0. In dual-address mode, the DMA
transfer halts after the completion of the write cycle that follows the initial read cycle in which
the address error occurs. DSAR, DAR and DTCR are updated by the final transfer.
Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in
DMAOR forcibly aborts the transfers on all channels at the end of the current bus cycle. The
TE bit is not set.