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When Instruction Fetch (after Instruction Execution) Is Specified as a Break Condition: The
value of the program counter (PC) saved in user break interrupt exception processing is the
address of the instruction following the instruction in which the break condition matches. The
fetched instruction is executed, and a user break interrupt occurs before the execution of the next
instruction. However, when a break is specified for a delay branch instruction, a delay slot
instruction is executed and a user break occurs before a branch destination instruction is executed.
The value of PC saved to the stack is the address of the branch destination instruction.
When Data Access (CPU or DMAC) Is Specified as a Break Condition: The program counter
(PC) value is the address of the instruction immediately following the last instruction executed
before the user break exception processing started. When data access (CPU or DMAC) is set as a
break condition, the place where the break will occur cannot be specified exactly. The break will
occur during an instruction fetched shortly after the break data access occurs.
6.3.7
PC Trace
PC trace is enabled by setting PCTE in BRCR to 1. When a branch (branch instruction, repeat, or
interrupt) occurs, an address from which the branch source can be calculated and a branch
destination address are stored in BRSR and BRDR respectively. The address of the last instruction
fetched and a pointer to the last instruction executed before the branch are stored in BRSR.
The address of the last-executed instruction before branching (IA) can be calculated from the
address and the pointer stored in BRSR. The expression for IA in terms of BSA (the address in
BRSR) and PID (the pointer in BRSR) is:
IA = BSA – 2
× PID
Some caution is required when doing an interrupt (branch) prior to the execution of the branch
destination instruction. In figure 6.2, the address of the instruction “Exec” executed immediately
before branching is calculated by IA = BSA – 2
× PID. However, when the “branch” has a delay
slot and the destination has an address of the form 4n + 2, BRSR is loaded with the address of the
branch destination “Dest” specified by the branch instruction. Because the calculation IA = BSA –
2
× PID does not apply to this case, the corresponding PID value is invalid. BSA only has a 4n + 2
boundary in this case; it is categorized as shown in table 6.3 for several cases.