![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_309.png)
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Bits 11 to 8—Resource Select 3–0 (RS3–RS0): Specify the sources of transfer requests to be sent
to the DMAC. Do not change the transfer request source unless the DMA enable bit (DE) is 0. The
RS3–RS0 bits are initialized to 0000 by a reset, in standby mode, or when the module standby
function is used.
Bit 11:
RS3
Bit 10:
RS2
Bit 9:
RS1
Bit 8:
RS0
Description
000
0
DREQ
(External request*1, dual address mode) (initial value)
0
1
Reserved (illegal setting)
001
0
DREQ
(External request*1, single-address mode*2)
001
1
DREQ
(External request*1, single-address mode*3)
0
1
0
RXI0 (On-chip SCI0 receive-data-full interrupt transfer request)*4
0
1
0
1
TXI0 (On-chip SCI0 transmit-data-empty interrupt transfer
request)*4
0
1
0
RXI1 (On-chip SCI1 receive-data-full interrupt transfer request)*4
0
1
TXI1 (On-chip SCI1 transmit-data-empty interrupt transfer
request)*4
1
0
RDFI0 (On-chip SIO0 receive-data-full interrupt transfer request)*4
1
0
1
TDEI0 (On-chip SIO0 transmit-data-empty interrupt transfer
request)*4
1
0
1
0
RDFI1 (On-chip SIO1 receive-data-full interrupt transfer request)*4
1
0
1
TDEI1 (On-chip SIO1 transmit-data-empty interrupt transfer
request)*4
1
0
Auto-request (Transfer requests automatically generated within
DMAC)*4
1
0
1
Reserved (illegal setting)
1
0
RDFI2 (On-chip SIO2 receive-data-full interrupt transfer request)*4
1
TDEI2 (On-chip SIO2 transmit-data-empty interrupt transfer
request)*4
Notes: 1. These settings are valid only in channels 0 and 1. None of these request sources can
be selected in channels 2 and 3.
2. Transfer from a memory-mapped external device or external memory to an external
device with a DACK pin.
3. Transfer from an external device with a DACK pin to a memory-mapped external device
or external memory.
4. Dual-address mode.
5. SCI0, SCI1: Serial communication interface channels 0 and 1.
SIO0–SIO2: Channels 0–2 of the serial interface.
Bit 7—Acknowledge Mode (AM): In dual-address mode, AM selects whether the DACK signal is
output during the data read cycle or write cycle. This bit is valid only for channels 0 and 1 external