![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_331.png)
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Bus Mode and Channel Priority: When a given channel is transferring in burst mode and there is
a transfer request to a different channel with a higher priority, the transfer of the second channel
will begin immediately. When the second channel is also operating in burst mode, the transfer of
the first channel will continue when the transfer of the second channel has completely finished.
When the second channel is in cycle-steal mode, the first channel will begin operating again after
the second channel completes the transfer of one unit, but the bus will then alternate between the
two channels. Because the first channel is in burst mode, the CPU will not get access to the bus.
This example is shown in figure 8.12.
DMAC
ch1
CPU
DMAC ch1
burst mode
DMAC ch1 burst mode
ch2 cycle-steal mode
ch2
ch1
ch2
DMAC ch1
burst mode
Bus
status
CPU
DMAC
ch1
DMAC
ch2
DMAC
ch1
DMAC
ch2
DMAC
ch1
DMAC
ch1
Note: Priority order is ch0 > ch3 > ch2 > ch1 (ch1 is burst mode and ch2 is
cycle-steal mode).
Figure 8.12 Bus Handling when Multiple Channels are Operating
8.3.5
Bus Cycle and
DREQ Signal Sample Timing
Bus Cycle Timing: The bus state controller (BSC) determines the number of states in a bus cycle
when the DMAC is the bus master, just as in the case when the CPU is the bus master. The wait
states of a bus cycle in single-address mode are determined by the DSWW1–DSWW0 and
DSWR1–DSWR0 fields of the BCR1 register in the BSC.
DREQ Signal Sample Timing: Normally, when the DREQ input is detected immediately prior to
the falling edge of the clock pulse (CLK) in external request mode, a DMAC bus cycle is
generated. The DMA transfer is performed three states later at the earliest. The sample timing after
DREQ input detection depends on bus mode, address mode, method of DREQ input detection, and
the clock mode.
DREQ signal sample timing in cycle-steal mode:
In cycle-steal mode the sample timing depends on whether
DREQ is detected by edge or level.
In the case of edge detection, once the falling edge of
DREQ is detected it will not be sampled
again until the next edge detection. When the
DREQ input is detected, the next sampling is not
executed until the first state in which a DACK signal is output. If a falling edge of the
DREQ
input is not detected with the next sample, the sampling then occurs with each CKM clock.
Figures 8.13 to 8.21 show the sampling timing of the
DREQ signal in the cycle-steal mode by
edge detection for each bus cycle.