296
Table 8.4
Selecting On-Chip Peripheral Module Request Modes with the RS3–RS0 Bits
RS3 RS2 RS1
RS0
DMA
Transfer
Request
Source
DMA Transfer
Request Signal
Source
Dest.
Bus
Mode
0
1
0
SCI0
receiver
RXI0 (SCI0 receive-data-full
interrupt transfer request)
SCRDR0
Any*
Cycle
steal
0
1
0
1
SCI0
transmitter
TXI0 (SCI0 transmit-data-
empty interrupt transfer
request)
Any*
SCTDR0
Cycle
steal
0
1
0
SCI1
receiver
RXI1 (SCI1 receive-data-full
interrupt transfer request)
SCRDR1
Any*
Cycle
steal
0
1
SCI1
transmitter
TXI1 (SCI1 transmit-data-
empty interrupt transfer
request)
Any*
SCTDR1
Cycle
steal
1
0
SIO0
receiver
RDFI0 (SIO0 receive-data-full
interrupt transfer request)
SIRDR0
Any*
Cycle
steal
1
0
1
SIO0
transmitter
TDEI0 (SIO0 transmit-data-
empty interrupt transfer
request)
Any*
SITDR0
Cycle
steal
1
0
1
0
SIO1
receiver
RDFI1 (SIO1 receive-data-full
interrupt transfer request)
SIRDR1
Any*
Cycle
steal
1
0
1
SIO1
transmitter
TDEI1 (SIO1 transmit-data-
empty interrupt transfer
request)
Any*
SITDR1
Cycle
steal
1
0
SIO2
receiver
RDFI2 (SIO2 receive-data-full
interrupt transfer request)
SIRDR2
Any*
Cycle
steal
1
SIO2
transmitter
TDEI2 (SIO2 transmit-data-
empty interrupt transfer
request)
Any*
SITDR2
Cycle
steal
Note:
SCI0, SCI1: Serial communication interface channels 0 and 1
SIO0–SIC2: Channels 0–2 of the serial interface
SCRDR0, SCRDR1: Receive data registers 0, 1 of SCI
SCTDR0, SCTDR1: Transmit data registers 0, 1 of SCI
SIRDR0–SIRDR2: Receive data registers 0–2 of SIO
SITDR0–SIRDR2: Transmit data registers 0–2 of SIO
Any: External memory, memory-mapped external device, on-chip memory, or on-chip
peripheral module (excluding BSC, SYSC, and DMAC)
Transfer signals from on-chip peripheral modules are interrupt requests, so the appropriate
interrupt enable bits in them must be set to output the interrupt signals. Transfer request signals
from on-chip peripheral modules (interrupt request signals) are not sent just to the DMAC, but