
xviii
Table 2.14
Instruction Formats for CPU Instructions...............................................................
61
Table 2.15
Instruction Formats for Double-Data Transfers......................................................
64
Table 2.16
Instruction Formats for Single-Data Transfers .......................................................
65
Table 2.17
Field A Parallel Data Transfer Instructions ............................................................
67
Table 2.18
Classification of CPU Instructions..........................................................................
70
Table 2.19
Instruction Code Formats........................................................................................
73
Table 2.20
Data Transfer Instructions ......................................................................................
74
Table 2.21
Arithmetic Instructions ...........................................................................................
76
Table 2.22
Logic Operation Instructions ..................................................................................
78
Table 2.23
Shift Instructions.....................................................................................................
79
Table 2.24
Branch Instructions .................................................................................................
80
Table 2.25
System Control Instructions....................................................................................
81
Table 2.26
Added CPU Instructions .........................................................................................
85
Table 2.27
Classification of DSP Data Transfer Instructions...................................................
86
Table 2.28
Double Data Transfer Instructions (X Memory Data)............................................
87
Table 2.29
Double Data Transfer Instructions (Y Memory Data)............................................
87
Table 2.30
Single Data Transfer Instructions ...........................................................................
88
Table 2.31
Correspondence between DSP Data Transfer Operands and Registers..................
89
Table 2.32
DSP Operation Instruction Formats........................................................................
90
Table 2.33
Correspondence between DSP Instruction Operands and Registers ......................
91
Table 2.34
Classification of CPU Instructions..........................................................................
92
Table 2.35
ALU Fixed Point Operation Instructions................................................................
93
Table 2.36
ALU Integer Operation Instructions .......................................................................
95
Table 2.37
MSB Detection Instructions....................................................................................
96
Table 2.38
Rounding Operation Instructions............................................................................
96
Table 2.39
ALU Logical Operation Instructions ......................................................................
97
Table 2.40
Fixed Point Multiplication Instructions ..................................................................
97
Table 2.41
Arithmetic Shift Operation Instructions..................................................................
98
Table 2.42
Logical Shift Operation Instructions ......................................................................
98
Table 2.43
System Control Instructions....................................................................................
99
Table 2.44
NOPX and NOPY Instruction Code Examples ...................................................... 100
Table 3.1
External Signals for the System Controller (SYSC)............................................... 104
Table 3.2
Registers of the System Controller (SYSC)............................................................ 104
Table 3.3
Clock Ratios when PLL Circuit Is Enabled............................................................ 106
Table 3.4
Clock Ratios when PLL Circuit Is Disabled........................................................... 107
Table 3.5
Clock Ratios when PLL Circuit Is Disabled........................................................... 108
Table 3.6
Clock Operating Modes .......................................................................................... 113
Table 3.7
Power-Down Modes ............................................................................................... 117
Table 4.1
Types of Exception Processing and Priorities ........................................................ 123
Table 4.2
Timing of Exception Source Detection and the Start of Exception Processing ..... 124
Table 4.3
Exception Processing Vector Tables ...................................................................... 126
Table 4.4
Exception Processing Vector Tables for IRQ Mode .............................................. 127
Table 4.5
Exception Processing Vector Tables for IRL Mode ............................................... 128