
xvi
Figure 10.9 Data Format in Clock Synchronous Mode.............................................................. 382
Figure 10.10 SCI Initialization Flowchart.................................................................................... 384
Figure 10.11 Serial Transmitting Flowchart ................................................................................ 385
Figure 10.12 SCI Transmit Operation Example .......................................................................... 386
Figure 10.13 Serial Receiving Flowchart..................................................................................... 388
Figure 10.14 SCI Receive Operation Example ............................................................................ 389
Figure 10.15 Serial Transmitting and Receiving Flowchart ........................................................ 391
Figure 10.16 Asynchronous Type Mode Receive Data Sampling Timing .................................. 394
Figure 10.17 Example of Clock Synchronous Type Send Using the DMAC.............................. 395
Figure 11.1 SIO Block Diagram ................................................................................................ 398
Figure 11.2 Receive: Interval Transfer Mode ............................................................................ 406
Figure 11.3 Receive: Continuous Transfer Mode ...................................................................... 407
Figure 11.4 Transmit: Interval Transfer Mode with TM = 0 ..................................................... 408
Figure 11.5 Transmit: Continuous Transfer Mode with TM = 0 ............................................... 409
Figure 11.6 Transmit: Interval Transfer Mode with TM = 1 ..................................................... 410
Figure 11.7 Transmit: Continuous Transfer Mode with TM = 1 ............................................... 411
Figure 12.1 Port A Configuration .............................................................................................. 413
Figure 12.2 Port B Configuration............................................................................................... 414
Figure 13.1 H-UDI Block Diagram............................................................................................ 428
Figure 13.2 Data I/O Timing (1) ................................................................................................ 435
Figure 13.3 Data I/O Timing (2) ................................................................................................ 436
Figure 13.4 Data I/O Timing (3) ................................................................................................ 436
Figure 13.5 Serial Data I/O ........................................................................................................ 438
Figure 14.1 CLK Output Timing................................................................................................ 447
Figure 14.2 EXTAL Clock Input Timing .................................................................................. 447
Figure 14.3 Oscillation Settling Time during Power On............................................................ 447
Figure 14.4 Oscillation Settling Time during Standby Recovery (Recovery Due to RST) ....... 448
Figure 14.5 Oscillation Settling Time during Standby Recovery (Recovery Due to NMI) ...... 448
Figure 14.6 PLL Synchronization Stabilization Time................................................................ 448
Figure 14.7 Reset Input Timing ................................................................................................. 449
Figure 14.8 Interrupt Signal Input Timing ................................................................................. 449
Figure 14.9 Basic Bus Cycle (No Waits) ................................................................................... 450
Figure 14.10 Basic Bus Cycle (External One Wait) .................................................................... 451
Figure 14.11 DRAM Bus Cycle (No Waits) ................................................................................ 452
Figure 14.12 DRAM Burst Mode Cycle (No Waits) ................................................................... 453
Figure 14.13 EDO DRAM Bus Cycle (No Waits)....................................................................... 454
Figure 14.14 CAS-before-RAS Cycle (No Waits)....................................................................... 455
Figure 14.15 Self-Refresh Cycle.................................................................................................. 456
Figure 14.16 PSRAM Bus Cycle (No Waits) .............................................................................. 457
Figure 14.17 PSRAM Auto-Refresh Cycle.................................................................................. 458
Figure 14.18 PSRAM Self Refresh Cycle.................................................................................... 459
Figure 14.19 Burst ROM Bus Cycle (No Burst Waits)................................................................ 460
Figure 14.20 FRT Input/Output Timing (CKE:CKP = 1:1)......................................................... 461