180
A user break is not issued if the address of the lower word of a 32-bit instruction is set as the break
condition. Consequently, the address of the upper word of the 32-bit instruction must be set as the
break address.
6.3.3
Break on Data Access Cycle
The memory cycles in which CPU data access breaks occur are:
Memory access cycles from instructions
Stacking and vector reads during exception processing
Table 6.2 shows, for each operand size, the range of bits in the break address register and address
bus that are compared to determine if the break condition is matched.
Table 6.2
Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Address Compared
Longword
Compares break address register bits 31–2 to address bus bits 31–2
Word
Compares break address register bits 31–1 to address bus bits 31–1
Byte
Compares break address register bits 31–0 to address bus bits 31–0
This means, for example, that when address H'00001003 is set without the operand size condition
specified (for example, the operand-size-select bits of the break bus cycle register are 00), the bus
cycle in which the break condition is satisfied include (assuming all other break conditions are
met):
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
When the data value is included in the break conditions on channel B: Specify either
longword, word or byte as the operand size in the break bus cycle registers (BBRA, BBRB). When
data values are included in break conditions, a break interrupt is generated when the address
conditions and data conditions match. When specifying an odd address with byte break data, write
the data in bits 7–0 of BDRB and configure the mask conditions in bits 7–0 of BDMRB. Bits 15–8
will have no influence on the break condition in this case. For an even address, write the data in
bits 15–8 of BDRB and configure the mask conditions in bits 15–8 of BDMRB. In this case, bits
7–0 will have no influence on the break condition. When a word or byte operand size is selected,
bits 31–16 of BDRB and BDMRB are ignored.
When the DMAC data access is included in the break condition: When the data value is not
included in the break condition for a DMAC data access, the operand size of the break bus cycle