![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_200.png)
178
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When
a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 by reading
BRDR.
DVF
Description
0
The value of BRDR is invalid
1
The valid of BRDR is valid
Bits 30–28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27–0—Branch Destination Address (BDA27–BDA0): These bits store the first fetched
address after branch.
6.3
Operation
6.3.1
Flow of the User Break Operation
The flow from the setting of break conditions to user break interrupt exception processing
proceeds as follows:
1. The break addresses are loaded into the break address registers (BARA, BARB), the masked
addresses are loaded into the break address mask registers (BAMRA, BAMRB), the break data
is loaded into the break data register (BDRB), and the masked data is loaded into the break
data mask register (BDMRB). The bus-break conditions are loaded into the break bus cycle
registers (BBRA, BBRB). The three pairs of control bits in BBRA and BBRB—CPU/DMAC
select, instruction fetch/data access select, and read/write select—are configured. No user
break interrupt will be generated if even one of these pairs of control bits is 00. The break
controls are loaded into the bits of BRCR.
2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the
interrupt controller, and the CPU condition match flags (CMFCA, CMFCB) and DMAC
condition match flags (CMFDA, CMFDB) for the respective channels are set.
3. The interrupt controller checks the user break interrupt’s priority. The user break interrupt has
priority 15, so it is accepted only if the interrupt mask level in bits I3–I0 in the status register
(SR) is 14 or lower. When the I3–I0 bit level is 15, the user break interrupt cannot be accepted
but it is held pending until user break interrupt exception processing can be carried out. Section
5, Interrupt Controller, describes the handling of priorities in greater detail.
4. When the priority permits acceptance of the user break interrupt, the CPU starts user break
interrupt exception processing.
5. The appropriate condition match flag (CMFCA, CMFDA, CMFCB, CMFDB) can be used to
check if the set conditions match or not. The flags are set by the matching of the conditions,
but they are not reset. 0 must first be written to them before they can be used again. If the
execution times break is specified for channel B, CMFCB or CMFDB is set when the number