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The TDRE bit of the serial status register (SSR) is a status flag that indicates that a transfer of
send data from the transmit data register (TDR) to the transmit shift register (TSR) has been
performed. The TDRE bit is set to 1 when the SCI transfers data from TDR to TSR.
Data writes to the TDR can be performed regardless of the status of the TDRE bit. However, if
new data is written to TDR while the status of the TDRE bit is 0, the data that was stored in the
TDR will be lost because it has not yet been transferred to the TSR. Therefore, writes of send
data to the TDR should always be performed only after confirming that the TDRE bit is set to
1.
2. Operation when multiple receive errors occur simultaneously:
When multiple receive errors occur simultaneously, the state of each of the SSR status flags
becomes as shown in table 10.11. Also, when an overrun error occurs, data transfer from the
receive shift register (RSR) to the receive data register (RDR) is not performed, so the receive
data is lost.
Table 10.11 SSR status flag states and receive data transfers
SSR Status Flag
Receive Data Transfer
Receive Error State
RDRF ORER FER
PER
RSR
→ RDR
Overrun error
1
0
X
Framing error
0
1
0
O
Parity error
0
1
O
Overrun error + framing error
1
0
X
Overrun error + parity error
1
0
1
X
Framing error + parity error
0
1
O
Overrun error + framing error + parity error 1
1
X
Note:
O: Receive data transferred from RSR
→ RDR.
X: Receive data not transferred from RSR
→ RDR.
3. Break detection and processing:
Breaks can be detected by reading directly the value of the RxD pin when a framing error
(FER) is detected. Since in breaks all the inputs from the RxD pin become 0, there are cases
where the FER bit is set, or cases where parity error (PER) is also set.
Since the SCI continues a receive operation even after a break is received, note that even if the
FER bit is cleared to 0 it will be set to 1 again.
4. Receive error flags and send operations (clock synchronous type mode only):
When the receive error flags (ORER, PER, FER) are set to 1, send cannot be started even by
setting the TDRE bit to 1. Always clear the receive error flags to 0 before starting a send.
Additionally, note that the receive error flags cannot be cleared to 0 even by clearing the RE
bit to 0.
5. Asynchronous type mode receive data sampling timing and receive margin: