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3.4.2
Sleep Mode
Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. On-chip peripheral
modules continue to run during sleep mode.
Four types of events cancel sleep mode:
Cancellation by an interrupt: When an interrupt occurs, sleep mode is canceled and interrupt
exception processing is executed. Sleep mode is not canceled if the interrupt cannot be
accepted because its priority is too low (see section 4.4.2, Interrupt Priority) or if an interrupt
by an on-chip peripheral module is disabled at the peripheral module.
Cancellation by a DMA address error: If a DMA address error occurs, sleep mode is canceled
and DMA address error exception processing is executed.
Cancellation by a power-on reset: A power-on reset cancels sleep mode.
Cancellation by a manual reset: A manual reset cancels the sleep mode.
3.4.3
Standby Mode
To enter standby mode, set the SBY bit to 1 in SBYCR, and then execute the SLEEP instruction.
The processor moves from program execution state to standby mode. A nonmaskable interrupt
(NMI) cannot be accepted during the five clocks that follow the execution of the SLEEP
instruction. In standby mode, power consumption is greatly reduced by halting not only the CPU,
but the clock and on-chip peripheral modules as well. The CPU register contents are held, but
some on-chip peripheral modules are initialized.
Three types of events cancel standby mode.
Cancellation by an NMI: When a rising edge or falling edge is detected in the NMI signal, the
clock is supplied to the entire chip, standby mode is canceled, and NMI exception processing
begins.
Cancellation by a power-on reset: A power-on reset cancels standby mode.
Cancellation by a manual reset: A manual reset cancels the standby mode.
3.4.4
Canceling Standby Mode
Standby mode is canceled by NMI interrupts, power-on resets, and manual resets.
Cancellation due to NMI interrupt input: When either a rising edge or falling edge of the
NMI signal (selected by the NMI edge select bit (NMIE) in the interrupt control register (ICR)
of the interrupt controller (INTC)) is detected, clock oscillation starts. This clock is supplied
only to the watchdog timer (WDT). A WDT overflow occurs when the time designated by the