
21
Supports CS-down mode, which maintains the assertion of the CS signal between burst
accesses
Table 1.2 shows the available memory interfaces for each of the external memory areas.
Table 1.2
BSC Memory Interfaces
External Memory Area
Memory Interface
CS0
Ordinary, burst ROM
CS1
Ordinary, burst ROM
CS2
Ordinary, DRAM
CS3
Ordinary, DRAM, pseudo-SRAM
Note:
In internal CS0 memory mode, the CS0 is mapped to on-chip memory.
Section 7 describes the BSC.
1.7.5
Direct Memory Access Controller (DMAC)
The direct memory access controller transfers data among memory (internal and external) and
peripheral devices (internal and external). The DMAC has the following features:
Four channels
Data transfer unit: Byte or word
Up to 65,536 data transfers per DMA request
Single-address mode transfers (channels 0–1): Either the source or destination of the transfer
(selectable) is accessed by a DACK signal, while the other is accessed by address. The transfer
of one datum requires one bus cycle. Supports transfers between:
An external device with a DACK signal and a memory-mapped external device
An external device with a DACK signal and external memory
Dual-address mode transfers (channels 0–3): Both the source and destination of the transfer are
accessed by address. Two data transfers are required; one from the transfer source to the
DMAC, and one from the DMAC to the transfer destination.
Transfer requests:
External request from DREQ pins (channels 0 and 1 only). DREQ can be detected either by
edge or by level
Requests from on-chip peripheral modules (serial communication interface (SCI), serial I/O
(SIO) )
Auto-request (the transfer request is generated automatically within the DMAC)
Selectable bus modes: Cycle-steal mode or burst mode
Selectable channel-priorities: Fixed, round-robin, or external-pin round-robin modes