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The CPU contains a fetch and decode unit, an integer unit, a DSP unit, and associated registers
(general, DSP, control, and system). The fetch and decode unit reads instructions and controls both
the integer and DSP units. The integer unit has the capabilities of an SH-2 CPU, with the addition
of some features to support DSP operations. The DSP unit performs advanced DSP functions and
has its own set of registers and separately addressable memory spaces called the X and Y
memories. The SH7410 instruction set is a version of the SH-2 instruction set that has been
enhanced to make full use of these additional architectural features. The CPU interfaces to
external logic through the peripheral modules, as shown on the right side of figure 1.1.
In addition to the external bus, the SH7410 processor has four internal buses:
Internal bus or I-bus (IAB, IDB): 32-bit address, 32-bit data
X-bus (XAB, XDB): 15-bit address, 16-bit data
Y-bus (YAB, YDB): 15-bit address, 16-bit data
Peripheral bus: 16-bit data
The I-bus transfers both instructions and data. The processor can access any region of address
space, including external space, through the I-bus. All MOV and MOVS operations use the I-bus.
MOVX operations use the X-bus, and MOVY operations use the Y-bus. The X- and Y-data buses,
XDB and YDB, can access only word data, so they are 16 bits wide.
The integer unit of the SH7410 processor uses the I-bus to transfer instructions and data (Von
Neumann architecture). The DSP unit also uses the I-bus to transfer instructions and data, but it
can also use the two additional internal buses, called the X-bus and Y-bus, to access data from the
X memory and Y memory simultaneously (extended-Harvard architecture).
The I-bus consists of a 32-bit address bus called IAB and a 32-bit data bus called IDB. The I-bus
can be used to address any memory space, including external memory and on-chip memory. When
accessing external memory, the I-bus connects to the external bus through the BSC.
The DSP unit has the X-bus and Y-bus available for data transfer operations. Each of these buses
consists of a 15-bit address bus, XAB or YAB, and a 16-bit data bus, XDB or YDB. The address
buses are only 15 bits wide because they can access only aligned word-length data, so the least-
significant bit of the 16-bit address is always zero. The processor uses the X-bus and Y-bus to
access X memory and Y memory data.
The SH7410 processor also has a peripheral bus for accessing peripheral modules through the
BSC. This 16-bit data bus allows the CPU and DMAC to access the memory-mapped registers in
the peripheral modules.
The UBC monitors the I-bus, X-bus, and Y-bus for break conditions. When a break condition is
met, an interrupt is requested.