vii
7.2.4
Individual Memory Control Register (MCR)....................................................... 204
7.2.5
Refresh Timer Control/Status Register (RTCSR) ................................................ 207
7.2.6
Refresh Timer Counter (RTCNT) ........................................................................ 208
7.2.7
Refresh Time Constant Register (RTCOR).......................................................... 209
7.3
Access Size and Data......................................................................................................... 209
7.4
Ordinary Space Interface ................................................................................................... 212
7.4.1
Direct Connection to Ordinary Space Devices .................................................... 212
7.4.2
Basic Timing ........................................................................................................ 215
7.4.3
Wait State Control ................................................................................................ 216
7.4.4
DMA Single-Address Transfers ........................................................................... 218
7.5
DRAM Interface ................................................................................................................ 219
7.5.1
Direct Connection to DRAM................................................................................ 219
7.5.2
Address Multiplex ................................................................................................ 221
7.5.3
Basic Timing ........................................................................................................ 222
7.5.4
Wait State Control ................................................................................................ 225
7.5.5
Burst Access ......................................................................................................... 228
7.5.6
DMA Single-Address Transfers ........................................................................... 238
7.5.7
Refresh.................................................................................................................. 254
7.5.8
Power-On Sequence ............................................................................................. 257
7.6
Pseudo-SRAM Interface.................................................................................................... 257
7.6.1
Direct Connection to Pseudo-SRAM ................................................................... 258
7.6.2
Basic Timing ........................................................................................................ 261
7.6.3
Wait State Control ................................................................................................ 263
7.6.4
Static-Column Access .......................................................................................... 265
7.6.5
Refresh.................................................................................................................. 267
7.6.6
Power-On Sequence ............................................................................................. 270
7.7
Burst ROM Interface ......................................................................................................... 270
7.8
Waits between Access Cycles ........................................................................................... 273
7.9
Bus Arbitration .................................................................................................................. 275
7.10
Precautions ........................................................................................................................ 277
Section 8 Direct Memory Access Controller (DMAC) ............................................ 279
8.1 Overview ................................................................................................................................ 279
8.2 Registers ................................................................................................................................. 282
8.2.1 DMA Source Address Register (DSAR) .................................................................. 283
8.2.2 DMA Destination Address Register (DAR) ............................................................. 284
8.2.3 DMA Transfer Count Register (DTCR) ................................................................... 284
8.2.4 DMA Channel Control Register (DCHCR).............................................................. 285
8.2.5 DMA Operation Register (DMAOR) ....................................................................... 290
8.3 Operation ................................................................................................................................ 292
8.3.1 DMA Transfer Flow ................................................................................................. 292
8.3.2 DMA-Transfer Requests .......................................................................................... 294
8.3.3 Channel Priority........................................................................................................ 297