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3.5.2
Using the WDT .................................................................................................... 121
Section 4 Exception Processing ....................................................................................... 123
4.1
Overview............................................................................................................................ 123
4.1.1
Types of Exception Processing and Priorities...................................................... 123
4.1.2
Exception Processing Operations ......................................................................... 124
4.1.3
Exception Processing Vector Table...................................................................... 125
4.2
Resets................................................................................................................................. 129
4.2.1
Types of Resets .................................................................................................... 129
4.2.2
Power-On Reset.................................................................................................... 129
4.2.3
Manual Reset........................................................................................................ 130
4.3
Address Errors ................................................................................................................... 131
4.3.1
Sources of Address Errors.................................................................................... 131
4.3.2
Address Error Exception Processing.................................................................... 131
4.3.3
Value of Stack Pointer (SP).................................................................................. 132
4.3.4
Value of Vector Base Register (VBR) ................................................................. 132
4.3.5
Address Errors Caused by Stacking of Address Error Exception Processing...... 132
4.4
Interrupts............................................................................................................................ 132
4.4.1
Interrupt Sources .................................................................................................. 132
4.4.2
Interrupt Priorities ................................................................................................ 133
4.4.3
Interrupt Exception Processing ............................................................................ 134
4.5
Exceptions Triggered by Instructions................................................................................ 134
4.5.1
Instruction-Triggered Exception Types................................................................ 134
4.5.2
Trap Instructions .................................................................................................. 135
4.5.3
Illegal Slot Instructions ........................................................................................ 135
4.5.4
General Illegal Instructions .................................................................................. 136
4.6
When Exception Sources Are Not Accepted..................................................................... 136
4.6.1
Immediately after a Delay Branch Instruction ..................................................... 136
4.6.2
Immediately after an Interrupt-Disabled Instruction............................................ 137
4.6.3
Instructions in a Repeat Loop............................................................................... 137
4.7
Stack Status when the Exception Service Routine Begins ................................................ 139
Section 5 Interrupt Controller (INTC) ........................................................................... 141
5.1
Overview............................................................................................................................ 141
5.1.1
Features ................................................................................................................ 141
5.1.2
Block Diagram...................................................................................................... 142
5.1.3
Pin Configuration ................................................................................................. 143
5.1.4
Register Configuration ......................................................................................... 143
5.2
Interrupt Sources................................................................................................................ 143
5.2.1
NMI Interrupts...................................................................................................... 144
5.2.2
User Break Interrupt ............................................................................................. 144
5.2.3
H-UDI Interrupt.................................................................................................... 144
5.2.4
External Interrupts................................................................................................ 144