![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_389.png)
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Bit 4—Framing Error (FER): In asynchronous mode, FER indicates that data reception ended
abnormally due to a framing error.
Bit 4: FER
Description
0
Reception is in progress or has ended normally (initial value)*1
Clear conditions:
Resets, during standby mode or module standby mode
When software reads FER after it has been set to 1 and then clears
FER to 0
1
A receive framing error occurred
Set condition: At the end of reception, when the final stop bit of the receive
data is checked by the SCI and found to be 0*2
Notes: 1. Clearing the RE bit to 0 in the serial control register (SCR) does not affect the FER bit,
which retains its previous value.
2. When the stop bit length is two bits, only the first bit is checked for a value of 1. When a
framing error occurs, the SCI transfers the receive data into the receive data register
(SCRDR), but does not set RDRF. Serial reception cannot continue while FER is set to
1. In clock synchronous mode, framing errors do not occur, but serial transmission
and/or reception is disabled if the FER flag is set.
Bit 3—Parity Error (PER): In asynchronous mode, PER indicates that data reception (with parity)
ended abnormally due to a parity error.
Bit 3: PER
Description
0
Reception is in progress or has ended normally (initial value)*1
Clear conditions:
Resets, during standby mode or module standby mode
When software reads PER after it has been set to 1, and then clears
PER to 0
1
A receive parity error occurred*2
Set condition: When the number of 1s in the receive data byte, including
the parity bit, does not match the even or odd parity setting of the parity
mode bit (O/E) in the serial mode register (SCMR)
Notes: 1. Clearing the RE bit to 0 in the serial control register (SCR) does not affect the PER bit,
which retains its previous value.
2. When a parity error occurs, the SCI transfers the receive data into the SCRDR, but
does not set RDRF. Serial reception cannot continue while PER is set to 1. In clock
synchronous mode, parity errors do not occur, but serial transmission and/or reception
is disabled if the PER flag is set.