
382
Synchronous
clock
Serial data
One unit (character or frame) of serial data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MSB
LSB
Transfer direction
Note: The serial clock is high, except during continuous transmitting or receiving.
Figure 10.9 Data Format in Clock Synchronous Mode
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed at the rising edge of the
serial clock. In each character, the serial data bits are transmitted in order from the least significant
bit (first) to the most significant bit (last). After output of the most significant bit, the
communication line remains in the state of that bit. In clock synchronous mode, the SCI receives
data by synchronizing with the rising edge of the serial clock. The data length is fixed at eight bits.
There are no start or stop bits. No parity bits can be added.
10.4.2
Clock
An internal clock generated by the on-chip baud-rate generator or an external synchronous clock
input from the SCK pin can be selected as the clock source. The clock source is selected by the
C/
A bit in the serial mode register (SCMR) and the CKE1–CKE0 field in the serial control register
(SCR).
When the SCI operates on an internal clock, it outputs the clock from the SCK pin. Eight
synchronous clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in the high state.
When an internal clock is selected, the SCI operates using the on-chip baud-rate generator and
outputs a synchronous clock signal to external devices.
When an external clock is selected, the SCI operates on the input synchronous clock. The on-
chip baud-rate generator is not used.