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Contents
Preface
..............................................................................................................................
i
Related Manuals ...........................................................................................................................
i
Section 1
Overview ...........................................................................................................
1
1.1
Features..............................................................................................................................
1
1.2
Architecture .......................................................................................................................
3
1.3
Pin Arrangement................................................................................................................
6
1.4
Pin Configuration ..............................................................................................................
7
1.5
Memory Map .....................................................................................................................
19
1.6
CPU....................................................................................................................................
21
1.6.1
Fetch and Decode .................................................................................................
21
1.6.2
Integer Unit ..........................................................................................................
22
1.6.3
DSP Unit ..............................................................................................................
22
1.7
Peripheral Module Units....................................................................................................
23
1.7.1
System Controller (SYSC) ...................................................................................
24
1.7.2
Interrupt Controller (INTC)..................................................................................
24
1.7.3
User Break Controller (UBC) ..............................................................................
25
1.7.4
Bus State Controller (BSC) ..................................................................................
25
1.7.5
Direct Memory Access Controller (DMAC)........................................................
27
1.7.6
Free-Running Timer (FRT) ..................................................................................
28
1.7.7
Serial Communication Interface (SCI) .................................................................
28
1.7.8
Serial I/O (SIO) ....................................................................................................
29
1.7.9
Pin Function Controller (PFC) .............................................................................
29
1.7.10 Hitachi User Debug Interface (H-UDI)................................................................
30
1.8
Processing States ...............................................................................................................
30
1.8.1
Program Execution State ......................................................................................
32
1.8.2
Exception Processing State ..................................................................................
32
1.8.3
Reset State ............................................................................................................
32
1.8.4
Power-Down State................................................................................................
32
1.8.5
Bus Release State .................................................................................................
34
Section 2 CPU ....................................................................................................................... 29
2.1
Register Configuration ......................................................................................................
29
2.1.1
General Registers..................................................................................................
29
2.1.2
Control Registers..................................................................................................
31
2.1.3
System Registers ..................................................................................................
34
2.1.4
DSP Registers .......................................................................................................
35
2.1.5
Cautions Concerning Guard Bits and Overflow Treatment .................................
37
2.1.6
Initial Values of Registers ....................................................................................
38