47
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branches: Such instructions as unconditional branches are delayed branch instructions.
In the case of delayed branch instructions, the branch occurs after execution of the instruction
immediately following the delayed branch instruction. This reduces pipeline disruption during
branching.
The branching operation of the delay branch occurs after execution of the slot instruction.
However, with the exception of such branch operations as register updating, execution of
instructions is performed with the order of delayed branch instruction, then delayed slot
instruction.
For example, even if the contents of a register storing a branch destination address are modified by
a delayed slot, the branch destination address will still be the contents of the register before the
modification.
Table 2.7
Delayed Branch Instructions
SH-DSP CPU
Description
Example of Conventional CPU
BRA
TRGET
ADD
R1,R0
Executes an ADD before
branching to TRGET
ADD.W
R1,R0
BRA
TRGET
Multiplication/Multiply-Accumulate Operation: 16
× 16 → 32 multiplications execute in one
to three cycles, and 16
× 16 + 64 → 64 multiply-accumulate operations execute in two to three
cycles. 32
× 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations
execute in two to four cycles.
T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and
conditional branches occur in accordance with its true or false status. The number of instructions
modifying the T bit is kept to a minimum to improve the processing speed.
Table 2.8
T Bit
SH-DSP CPU
Description
Example of Conventional CPU
CMP/GE
R1,R0
BT
TRGET0
BF
TRGET1
T bit is set when R0
≥ R1. The
program branches to TRGET0 when
R0
≥ R1 and to TRGET1 when
R0 < R1.
CMP.W
R1,R0
BGE
TRGET0
BLT
TRGET1
ADD
#–1,R0
CMP/EQ
#0,R0
BT
TRGET
T bit is not changed by ADD. T bit
is set when R0 = 0. The program
branches when R0 = 0.
SUB.W
#1,R0
BEQ
TRGET