![](http://datasheet.mmic.net.cn/120000/SH7410_datasheet_3575231/SH7410_198.png)
176
Bit:
7
6
5
4
3
2
1
0
Bit name:
Initial value:
0
R/W:
R/W
When the execution times break condition of channel B is enabled (by setting the ETBE bit in
BRCR), this 16-bit register specifies the number of times a channel B break condition occurs
before a user break interrupt is requested. The maximum number is 212 – 1 times. A power-on
reset initializes BETR to H'0000. Each time a channel B break condition is satisfied, BETR is
decremented by one. An interrupt is requested when a break condition is satisfied after the BETR
has decreased to H'0001.
No exceptions or interrupts are accepted for instructions in a repeat loop having less than four
instructions (see section 4.6, When Exception Sources Are Not Accepted). Therefore, BETR is not
decremented for break condition matches that occur for instructions in a repeat loop of less than
four instructions.
Bits 15–12 are always read as 0, and 0 should always be written in these bits.
6.2.11
Branch Source Register (BRSR)
Bit:
31
30
29
28
27
26
25
24
Bit name:
SVF
PID2
PID1
PID0
BSA27
BSA26
BSA25
BSA24
Initial value:
0
*
R/W:
R
Bit:
23
22
21
…
3
2
1
0
Bit name:
BSA23
BSA22
BSA21
…
BSA3
BSA2
BSA1
BSA0
Initial value:
*
…
*
R/W:
R
…
R
Note:
Not initialized by reset.
The BRSRs are a set of four 32-bit read only registers that store the lower 28-bits of the last-
fetched address before a branch. They also store 3-bit pointers that indicate the number of cycles
from fetch to execution for the last executed instruction. These quantities are used during PC trace
(see section 6.3.7, PC Trace) to calculate the address of the last executed instruction before the
branch. The BRSRs form a FIFO (first-in-first-out) queue for PC trace. The queue shifts during
each branch. The BRSRs have a flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when a BRSR is read or when BRSR is initialized by power-on reset or manual reset.
Other bits are not initialized by reset.