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Figure 7.36 DMA Single-Address Transfer Timing for EDO DRAM (Write with Wait) ........ 248
Figure 7.37 RAS Down Mode: DMA Single-Address Transfer Timing (Same Row Access,
Read, with Wait) ..................................................................................................... 249
Figure 7.38 RAS Down Mode: DMA Single-Address Transfer Timing for EDO DRAM
(Same Row Access) ................................................................................................ 250
Figure 7.39 DMA Single-Address Transfer Timing for EDO DRAM (Burst Mode, Read) ..... 251
Figure 7.40 DMA Single-Address Transfer Timing for EDO DRAM (Burst Mode,
Read with Wait) ...................................................................................................... 252
Figure 7.41 DMA Single-Address Transfer Timing for EDO DRAM (Burst Mode, Write) .... 253
Figure 7.42 DMA Single-Address Transfer Timing for EDO DRAM (Burst Mode,
Write with Wait) ..................................................................................................... 254
Figure 7.43 DRAM CAS-Before-RAS Refresh Timing (No Wait)........................................... 255
Figure 7.44 DRAM CAS-Before-RAS Refresh Timing (with Wait) ........................................ 256
Figure 7.45 DRAM Self-Refresh Timing .................................................................................. 257
Figure 7.46 Example of a Connection to a 1-Mbit Pseudo-SRAM............................................ 259
Figure 7.47 Example of a Connection to a 4-Mbit Pseudo-SRAM............................................ 260
Figure 7.48 Basic Timing of a Pseudo-SRAM Access .............................................................. 262
Figure 7.49 Pseudo-SRAM Access with Added Waits.............................................................. 264
Figure 7.50 Static-Column Access Timing of Pseudo-SRAM .................................................. 266
Figure 7.51 Pseudo-SRAM Auto-Refresh Timing (No Wait) ................................................... 268
Figure 7.52 Pseudo-SRAM Auto-Refresh Timing (With Waits)............................................... 269
Figure 7.53 Pseudo-SRAM Self-Refresh Timing ...................................................................... 270
Figure 7.54 Burst ROM Access (Two Ordinary Waits and No Burst Waits)............................ 271
Figure 7.55 CS-Down Mode: Burst ROM Access ..................................................................... 272
Figure 7.56 Basic Access Cycle (Following CS Down State) ................................................... 273
Figure 7.57 Waits between Access Cycles ................................................................................ 275
Figure 7.58 Bus Arbitration Timing........................................................................................... 277
Figure 8.1
DMAC Block Diagram ........................................................................................... 281
Figure 8.2
DMA Transfer Flowchart ....................................................................................... 293
Figure 8.3
Round-Robin Mode ................................................................................................ 298
Figure 8.4
Changes in Priority with Round-Robin Mode ........................................................ 300
Figure 8.5
Changes in Priority with External-Pin Round-Robin Mode ................................... 301
Figure 8.6
Data Flow in Single Address Mode........................................................................ 303
Figure 8.7
Example of Single-Address Mode DMA Transfer Timing .................................... 304
Figure 8.8
Data Flow in Dual-Address Mode .......................................................................... 305
Figure 8.9
Dual-Address Mode DMA Transfer Timing .......................................................... 306
Figure 8.10 Cycle-Steal Mode DMA Transfer Example ........................................................... 306
Figure 8.11 Burst Mode DMA Transfer Example ..................................................................... 307
Figure 8.12 Bus Handling when Multiple Channels are Operating ........................................... 309
Figure 8.13
DREQ Sampling Timing (Cycle-Steal, Single-Address, DREQ Edge Detection,
CKM:CLK = 1:1).................................................................................................... 310
Figure 8.14
DREQ Sampling Timing (Cycle-Steal, Single-Address, DREQ Edge Detection,
CKM:CLK = 2:1).................................................................................................... 310