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Section 1 Overview
1.1
Features
The SH7410 processor is a single-chip device that combines the functionality of a full-fledged
reduced instruction set computer (RISC) processor and a full-fledged digital signal processing
(DSP) processor. It is ideally suited for applications that require both microcontroller and DSP-
type processing. Traditionally, such applications have required the use of two chips: a
microcontroller and a DSP chip. The SH7410 processor offers an economical, one-chip solution
for such applications.
The SH7410 single-chip solution lowers development and operating costs. The unified memory
and single instruction stream simplify the design. Use of a single processor removes the need to
support inter-processor communication. Moreover, a single processor needs only one emulator.
Power consumption can also be reduced through the special power-down states.
The SH7410 is upwardly compatible with the Hitachi SH-1 and SH-2 object code. While the SH-2
processors provide basic DSP capabilities such as the multiply-accumulate functionality, the
SH7410 processor provides a full DSP-type data bus and advanced DSP operations, including
single-cycle 16-bit by 16-bit signed multiplication, barrel shifting, priority encoding, rounding,
and modulo addressing. The processor performs DSP operations in fixed-point arithmetic,
providing guard bits to protect against overflows.
The SH7410 processor uses a RISC architecture like that of the SH-2 family of processors. By
using a five-stage pipeline system, it can execute most instructions in a single processor clock
cycle, thus providing very high performance. Its enhanced instruction set consists of all of the
SH-2 instructions plus many extensions for DSP programming. These include parallel DSP
instructions, which execute multiple operations simultaneously, zero-overhead loop control,
modulo addressing, and dual addressing.
The SH7410 processor uses both a standard Von Neumann architecture (both instructions and data
share a single bus) for the integer unit and an extended Harvard architecture (instructions and data
have separate buses) for the DSP unit. The Harvard architecture allows simultaneous access to the
program code and to two on-chip memory spaces, called X memory and Y memory, for the
efficient implementation of DSP algorithms.
This manual describes all of the hardware features of the SH7410 processor, with emphasis on
interfacing to the processor through the many on-chip peripheral modules.
The features of the SH7410 processor include:
Architecture
Original Hitachi architecture