ix
10.2
Registers ............................................................................................................................ 358
10.2.1 Receive Shift Register (SCRSR).......................................................................... 358
10.2.2 Receive Data Register (SCRDR).......................................................................... 358
10.2.3 Transmit Shift Register (SCTSR) ........................................................................ 358
10.2.4 Transmit Data Register (SCTDR) ........................................................................ 359
10.2.5 Serial Mode Register (SCMR) ............................................................................. 359
10.2.6 Serial Control Register (SCR).............................................................................. 362
10.2.7 Serial Status Register (SCSR) .............................................................................. 365
10.2.8 Bit Rate Register (SCBRR).................................................................................. 368
10.3
Asynchronous Operation ................................................................................................... 372
10.3.1 Formats ................................................................................................................. 372
10.3.2 Clock .................................................................................................................... 374
10.3.3 Initialization.......................................................................................................... 374
10.3.4 Serial Data Transmission...................................................................................... 375
10.3.5 Reception.............................................................................................................. 378
10.4
Clock Synchronous Operation ........................................................................................... 381
10.4.1 Format .................................................................................................................. 381
10.4.2 Clock .................................................................................................................... 382
10.4.3 Initialization.......................................................................................................... 383
10.4.4 Serial Data Transmission...................................................................................... 384
10.4.5 Serial Data Reception ........................................................................................... 386
10.4.6 Simultaneous Transmission and Reception of Serial Data................................... 389
10.5
SCI Interrupt Sources and the DMAC............................................................................... 392
10.6
Cautions on Use................................................................................................................. 392
Section 11 Serial I/O (SIO) ............................................................................................... 397
11.1
Overview............................................................................................................................ 397
11.1.1 Features ................................................................................................................ 397
11.2
Register Configuration ...................................................................................................... 399
11.2.1 Receive Shift Register (SIRSR) ........................................................................... 400
11.2.2 Receive Data Register (SIRDR) ........................................................................... 401
11.2.3 Transmit Shift Register (SITSR).......................................................................... 401
11.2.4 Transmit Data Register (SITDR).......................................................................... 402
11.2.5 Serial Control Registers (SICTR) ........................................................................ 402
11.2.6 Serial Status Register (SISTR) ............................................................................. 404
11.3
Operation ........................................................................................................................... 406
11.3.1 Input...................................................................................................................... 406
11.3.2 Output ................................................................................................................... 407
11.4
SIO Interrupt Sources and the DMAC .............................................................................. 411
11.5
Cautions on Use................................................................................................................. 412
Section 12 Pin Function Controller (PFC).................................................................... 413
12.1
Overview............................................................................................................................ 413