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8.3.4 DMA Transfer Types................................................................................................ 301
8.3.5 Bus Cycle and
DREQ Signal Sample Timing.......................................................... 309
8.3.6 DMA Transfer End Conditions ................................................................................ 329
8.4 Examples ................................................................................................................................ 330
8.4.1 Transfer between On-Chip SCI and External Memory ............................................ 330
8.4.2 Cautions .................................................................................................................... 330
Section 9 16-Bit Free-Running Timer (FRT) .............................................................. 331
9.1
Overview............................................................................................................................ 331
9.1.1
Features ................................................................................................................ 331
9.1.2
Block Diagram...................................................................................................... 331
9.1.3
Pin Configuration ................................................................................................. 332
9.1.4
Register Configuration ......................................................................................... 333
9.2
Description of Registers .................................................................................................... 335
9.2.1
Free-Running Counter (FRC)............................................................................... 335
9.2.2
Output Compare Registers A and B (FOCRA and FOCRB) ............................... 336
9.2.3
Input Capture Register (FICR) ............................................................................. 336
9.2.4
Free-Running Timer Control/Status Register (FTCSR)....................................... 337
9.2.5
Timer Control Register 0–2 (FTCR0–FTCR2) .................................................... 339
9.3
CPU Interface .................................................................................................................... 340
9.4
Operation ........................................................................................................................... 342
9.4.1
FRC Count Timing ............................................................................................... 342
9.4.2
Output Timing for Output Compare..................................................................... 343
9.4.3
FRC Clear Timing ................................................................................................ 344
9.4.4
Input Capture Timing ........................................................................................... 344
9.4.5
Input Capture Flag (ICF) Set Timing ................................................................... 345
9.4.6
Output Compare Flag (OCFA, OCFB) Set Timing.............................................. 346
9.4.7
Timer Overflow Flag (OVF) Set Timing ............................................................. 347
9.5
Interrupt Sources................................................................................................................ 347
9.6
Example of FRT Use ......................................................................................................... 349
9.7
Cautions on Use................................................................................................................. 350
9.7.1
Contention between FRC Writes and Clears........................................................ 350
9.7.2
Contention between FRC Writes and Increments ................................................ 351
9.7.3
Contention between FOCR Writes and Compare Matches.................................. 352
9.7.4
Internal Clock Switching and Counter Operation ................................................ 353
9.7.5
Timer Output (FTOA, FTOB).............................................................................. 353
Section 10 Serial Communication Interface (SCI) .................................................... 355
10.1
Overview............................................................................................................................ 355
10.1.1 Features ................................................................................................................ 355
10.1.2 Block Diagram...................................................................................................... 356
10.1.3 Pin Configuration ................................................................................................. 356
10.1.4 Register Configuration ......................................................................................... 357