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1.6.2
Integer Unit
The integer unit of the SH7410 processor is a version of the SH-2 CPU core that has been
enhanced to support DSP operations. It can execute all SH-1 and SH-2 object code, but it is not
upwardly compatible with SH-3 object code. Compared with the SH-2 CPU core, the integer unit
of the SH7410 processor offers the following additional features:
Dual-Addressing Capability: The SH7410 processor supports the simultaneous access of data
from two on-chip memory locations by using the main integer unit ALU to calculate the X
memory address and a separate 16-bit ALU called the pointer arithmetic unit (PAU) to calculate
the Y memory address.
Index Addressing with Pointer Update: The SH7410 addressing mechanism supports index
addressing with automatic updating of the address pointer. The address pointer is automatically
incremented or decremented by 2 or 4 to access sequential words or longwords in memory, or
incremented by a specified index amount after each memory access.
Modulo Addressing: Modulo addressing is useful for implementing circular buffers. The starting
and ending modulo addresses are specified in the MOD control register. When the address register
is incremented to the ending address, it is automatically reset to the starting address.
Zero-Overhead Loop Control: The SH7410 processor supports zero-overhead program loops,
that is, loops in which no time is spent incrementing counters or testing for the completion of loop
cycles. These loops are important for high-speed DSP applications. To set up such a loop, special-
purpose registers are used to specify the repeat count, the starting address, and the ending address
of the instruction loop. Then, the processor automatically executes the loop the specified number
of times.
1.6.3
DSP Unit
The SH7410 CPU has a powerful DSP unit that can execute up to two operations in parallel,
providing faster DSP performance than conventional multiply-accumulate (MAC) units. The DSP
unit offers the following features:
Parallel Operations: The DSP unit can execute up to two independent operations simultaneously:
one addition or subtraction operation and one multiply operation. Simultaneously, the integer unit
can execute up to two load or store operations concerning X memory or Y memory. A single 32-
bit instruction specifies these four operations.
32-/40-Bit Data Registers: The DSP unit uses a set of eight data registers: two 40-bit registers
and six 32-bit registers. The upper eight bits of the 40-bit registers serve as guard bits to
accommodate overflow results in certain operations.