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Appendix D Precautions During Programming.......................................................... 488
Appendix E Precautions on Using the UBC and H-UDI ......................................... 490
E.1
Contents ............................................................................................................................. 490
E.2
Precautions on Use ............................................................................................................ 490
Appendix F External Dimensions ................................................................................... 491
Figures
Figure 1.1
SH7410 Block Diagram..........................................................................................
4
Figure 1.2
SH7410 Pin Arrangement (FP-176) .......................................................................
6
Figure 1.3
Memory Map for Internal CS0 Memory Mode ......................................................
14
Figure 1.4
Memory Map for External CS0 Memory Mode .....................................................
15
Figure 1.5
Transitions Between SH7410 Processing States ....................................................
25
Figure 2.1
General Register Configuration ..............................................................................
30
Figure 2.2
Control Register Configuration ..............................................................................
32
Figure 2.3
System Register Configuration ...............................................................................
34
Figure 2.4
DSP Register Configuration ...................................................................................
36
Figure 2.5
Register Data Format ..............................................................................................
39
Figure 2.6
Data Formats in Memory........................................................................................
39
Figure 2.7
DSP Type Data Formats .........................................................................................
41
Figure 2.8
DSP Register-Bus Relationship during Data Transfers..........................................
46
Figure 2.9
X, Y Data Transfer Addressing ..............................................................................
55
Figure 2.10 Single Data Transfer Addressing............................................................................
56
Figure 2.11 Modulo Addressing ................................................................................................
57
Figure 2.12 Instruction Formats for DSP Instructions ...............................................................
64
Figure 2.13 Field B ALU Operation Instructions, Multiplication Instructions..........................
69
Figure 3.1
Block Diagram of System Controller ..................................................................... 102
Figure 3.2
Example of Organizing a Crystal Oscillator........................................................... 114
Figure 3.3
Connecting an External Clock ................................................................................ 115
Figure 3.4
Cautions When Using a PLL Oscillator Circuit ..................................................... 115
Figure 3.5
Cautions on Using the PLL’s Oscillation Circuit ................................................... 116
Figure 3.6
Use of NMI Interrupts to Release Standby Mode .................................................. 120
Figure 3.7
Block Diagram of the WDT.................................................................................... 121
Figure 4.1
Limitations on Interrupt Acceptance in Repeat Mode............................................ 138
Figure 5.1
INTC Block Diagram.............................................................................................. 142
Figure 5.2
Example of Connections for External Vector Mode Interrupts.............................. 146
Figure 5.3
Example of Connections for Auto Vector Mode Interrupts.................................... 146
Figure 5.4
External Vector Mode Interrupt Vector Fetch Cycle.............................................. 147
Figure 5.5
Interrupt Sequence Flowchart ................................................................................. 157
Figure 5.6
Stack after Interrupt Exception Processing............................................................. 158
Figure 5.7
Example of Pipeline Operation when an IRQ Interrupt is Received...................... 160
Figure 5.8
Interrupt Response Block Diagram ........................................................................ 161