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4.1.2
Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing
shown in table 4.2.
Table 4.2
Timing of Exception Source Detection and the Start of Exception Processing
Exception Processing
Timing of Source Detection and Start of Processing
Reset
Power-on reset
Detected when the NMI signal is high; processing starts
immediately upon the RST pin changing from low to high
Manual reset
Detected when the NMI signal is low; when the RST pin
changes from low to high, processing starts during the next
separation between bus cycles
Address error
Detected when instruction is decoded and starts when the
previously executing instruction finishes executing
Interrupt
Detected when an instruction is decoded and starts when the
previous instruction finishes executing
Instructions
Trap instruction
Starts from the execution of a TRAPA instruction
General illegal
instructions
Starts from the decoding of undefined code* anytime except
after a delay branch instruction (delay slot)
Illegal slot
instructions
Starts from the decoding of undefined code* placed directly
following a delay branch instruction (delay slot) or of instructions
that rewrite the PC
Note:
No general illegal instruction or illegal slot instruction exception processing is executed for
DSP instruction format (double data transfer instruction, single data transfer instruction,
parallel processing instruction) undefined codes.
When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception processing vector table (PC and SP are respectively located at the H'00000000 and
H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for
manual resets). See section 4.1.3, Exception Processing Vector Table, for more information. 0
is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits
(I3–I0) of the status register (SR). The program begins running from the PC address fetched
from the exception processing vector table.