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7.6.5
Refresh
When the RMODE bit in the MCR is cleared to 0 and the RFSH bit is set to 1, the BSC performs a
scattered refresh of the pseudo-SRAM using the auto-refresh cycle. Refreshes are performed at
intervals determined by the value selected by the CKS2–CKS0 field in RTCSR and the value in
RTCOR. Choose the values of RTCOR and the CKS2–CKS0 field so that they satisfy the refresh
interval specifications of the pseudo-SRAM being used. First, write values into the RTCOR,
RTCNT, and the RMODE, RFSH bits in MCR. Then write the CKS2–CKS0 bits. RTCNT starts
incrementing when a clock is selected with the CKS2–CKS0 field. The BSC constantly compares
the RTCNT value to the RTCOR value and generates a request for a refresh when the two match,
starting an auto-refresh cycle. RTCNT is cleared to 0 at that time, and the count-up begins again.
Figure 7.51 shows the timing for an auto-refresh cycle.
The RCD1–RCD0 field in the MCR and the W31 and W30 bits in the WCR specify the number of
OE/RFSH or RFSH assertion states for an auto-refresh cycle. Like ordinary space accesses, the
TRP1–TRP0 field in the MCR specifies the precharge time from the negation of
OE/RFSH or
RFSH to the next assertion of CE. Figure 7.52 shows the addition of wait states to the auto-refresh
cycle (Tpw, Trw, and Tw).
Pseudo-SRAM initializes self-refresh mode (figure 7.53) when the
RFSH signal stays low for a
prescribed period. Start self-refresh by setting the RMODE and RFSH bits in the MCR to 1.
During the self-refresh, the pseudo-SRAM cannot be accessed. To clear the self-refresh, clear
either the RMODE or RFSH bit to 0. After a self-refresh is done, immediately write values to
MCR, RTCSR, RTCOR, and RTCNT so that the auto-refresh is performed at the correct interval.
However, to ensure correct self-refresh release, it is necessary to wait the prescribed amount of
time between the negation of the
RFSH signal and the performance of the auto-refresh.