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When using EDO burst mode when CKM:CKE = 1:1, make the EDO connected bus width 32
bit.
2. External bus right requests when in DRAM RAS-down mode when CKM:CKE = 1:1 (CKM
and CKE clock are the same).
Bus right requests from outside of the chip are not supported in DRAM RAS-down mode, so
please do not use them. This is applicable for all cases where the CKM and CKE clock ratio is
one.
To issue a bus right request from outside of the chip during DRAM RAS-down mode
execution when CKM:CKE = 1:1 (CKM and CKE clock are the same), issue the bus right
request after canceling DRAM RAS-down mode.
3. Refresh function in CS-down mode:
The refresh function is not supported in burst ROM CS CS-down mode, so please do not use it.
To use the refresh function when in burst ROM CS CS-down mode, first cancel the burst ROM
CS CS-down mode, then use the refresh function.
4.
BS signal:
Since momentary narrow pulse-type glitches may be output on the
BS signal, do not use the
BS signal as a trigger signal (clock signal) for latches, etc.
5. Ordinary space interface:
Concerning the
RD signal [illegible], match with the specs of the SRAM used and insert an
external circuit between the SH7410 and the SRAM.
6. Operation of the
RAS signal when an access to on-chip memory occurs during execution of an
EDO DRAM RAS CS-down mode write access:
When the CKM:CKE is other than = 1:1 (CKM and CKE clock are not the same), the
RAS
signal is negated even when an on-chip memory access occurs during execution of an EDO
DRAM RAS CS-down mode write access. There is no problem in accessing memory.
Additionally, when an on-chip memory access occurs during execution of an EDO DRAM
RAS CS-down mode write access when CKM:CKE = 1:1 (CKM and CKE clock are the same),
as well as when an on-chip memory access occurs during execution of an EDO DRAM RAS
CS-down mode read access regardless of the CKM and CKE clock ratio, the
RAS signal
remains asserted.