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of execution times matches with the number of execution times specified by BETR. If the
break condition is set for both CPU and DMAC data access, the flag set is determined by
whether the last condition match involved a CPU or DMAC access.
6. In sequential break mode, a condition match flag for channel A is set when break condition of
channel A is satisfied. A condition match flag for channel B is set when channel B break
condition matches after a prior channel A break condition match, but is not set either before, or
at the same time as, a channel A break condition match.
6.3.2
Break on Instruction Fetch Cycle
When CPU/instruction fetch/read is set in the break bus cycle registers (BBRA/BBRB), the break
condition becomes the CPU’s instruction fetch cycle. The operand size in the break bus cycle
register does not need to be specified. Whether it then breaks before or after the execution of the
instruction can then be selected with the PCBA, PCBB bits of the break control register (BRCR)
for the appropriate channel.
When an instruction fetch condition that is set for a break before execution is matched, the break
occurs when it is confirmed that the instruction has been fetched and will be executed. Therefore
this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or
during an interrupt transition, but not executed). When this kind of break is set for the delay slot of
a delay branch instruction or for an instruction following an interrupt-disabled instruction such as
LDC, the interrupt is not generated until just before execution of the first instruction that accepts
the interrupt.
Reads to and writes from UBC registers are done in the MA (memory access) stage of the
instruction pipeline. No user break can be generated on a new break condition until the new break
condition is written into the break address register during the MA stage. If the fetch stage of a
subsequent instruction occurs before the new break condition address is written into the break
address register, a break will not be generated even if the fetched address matches the break
condition address that is to be loaded in to the break address register. To ensure that a UBC
register has been updated with a new value, do a read from the newly-written register. Instructions
after the register read will be valid for the newly-written register value.
When the break condition stipulates that the break occur after instruction execution, the instruction
that matched the break condition is executed, and then the interrupt is generated prior to the
execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun
fetch instructions. When this kind of break is set for a delay branch instruction or an interrupt-
disabled instruction such as LDC, the interrupt is not generated until the first instruction that
accepts the interrupt.
When the instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored.
There is thus no need to set break data for the break of the instruction fetch cycle.