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5.2.5
On-Chip Peripheral Module Interrupts ................................................................ 147
5.2.6
Interrupt Exception Vectors and Priority.............................................................. 148
5.3
Registers ............................................................................................................................ 153
5.3.1
Interrupt Priority Registers A–D (IPRA–IPRD) .................................................. 153
5.3.2
Interrupt Control Register (ICR) .......................................................................... 154
5.4
Interrupt Operation ............................................................................................................ 155
5.4.1
Interrupt Sequence................................................................................................ 155
5.4.2
Stack after Interrupt Exception Processing .......................................................... 157
5.5
Interrupt Response Time.................................................................................................... 158
5.6
Sampling of the IRQ3–IRQ0 Signals in IRL Mode .......................................................... 160
Section 6 User Break Controller (UBC)........................................................................ 163
6.1
Overview............................................................................................................................ 163
6.2
Registers ............................................................................................................................ 165
6.2.1
Break Address Register A (BARA) ..................................................................... 165
6.2.2
Break Address Mask Register A (BAMRA)........................................................ 166
6.2.3
Break Bus Cycle Register A (BBRA) .................................................................. 166
6.2.4
Break Address Register B (BARB)...................................................................... 168
6.2.5
Break Address Mask Register B (BAMRB) ........................................................ 168
6.2.6
Break Data Register B (BDRB) ........................................................................... 169
6.2.7
Break Data Mask Register B (BDMRB).............................................................. 170
6.2.8
Break Bus Cycle Register B (BBRB) .................................................................. 170
6.2.9
Break Control Register (BRCR) .......................................................................... 172
6.2.10 Execution Times Break Register (BETR) ............................................................ 175
6.2.11 Branch Source Register (BRSR) .......................................................................... 176
6.2.12 Branch Destination Register (BRDR) .................................................................. 177
6.3
Operation ........................................................................................................................... 178
6.3.1
Flow of the User Break Operation........................................................................ 178
6.3.2
Break on Instruction Fetch Cycle ......................................................................... 179
6.3.3
Break on Data Access Cycle ................................................................................ 180
6.3.4
Break on X- or Y-Memory Bus Cycle ................................................................. 181
6.3.5
Sequential Break .................................................................................................. 181
6.3.6
Value of Saved Program Counter......................................................................... 181
6.3.7
PC Trace ............................................................................................................... 182
6.3.8
Examples .............................................................................................................. 184
6.3.9
Cautions................................................................................................................ 191
Section 7 Bus-State Controller (BSC) ........................................................................... 193
7.1
Overview............................................................................................................................ 193
7.2
Registers ............................................................................................................................ 197
7.2.1
Bus Control Register 1 (BCR1)............................................................................ 198
7.2.2
Bus Control Register 2 (BCR2)............................................................................ 201
7.2.3
Wait Control Register (WCR).............................................................................. 202