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In clock operating modes 0–2, when the PLL circuit is enabled, it quadruples the external
source clock frequency. As a result, the obtainable CKI frequency becomes four times that of
the external source clock frequency. When the PLL circuit is disabled, CKI uses the external
source (crystal oscillator or external clock input) as is.
2. In operating mode 3, DIV1 halves the external source clock frequency. DIV1 is not enabled in
other operating modes. In clock operating mode 3, when the PLL circuit is enabled, it
quadruples the DIV1 output signal. As a result, the obtainable CKI frequency becomes twice
that of the external clock input frequency. When the PLL circuit is disabled, CKI becomes half
of the external clock input frequency.
Definition of terms:
External source: Crystal oscillator or external clock signal generator
External source clock: Crystal oscillator output or external clock input signal (in other words,
external source output signal)
In operating modes 4 and 5, the PLL circuit is always enabled, making the frequency of CKI four
times that of the external source. The DIV1 is disabled in these modes.
The internal clock divider, DIV2, generates the clocks CKM, CKE, and CKP from CKI. The ratios
of the frequencies generated by DIV2 for these three clocks are specified by control bits SCK3 to
SCK0 (bits 3–0) in FRQMR. The initial values after a reset of bits SCK3–SCK0 are specified by
signals MD2–MD0, as shown in table 3.6. Signals MD2–MD0 must be in one of the valid
configurations given in table 3.6 at reset and should not be changed during operation.
Table 3.6 summarizes the functions of the clock operating modes. Modes not defined in table 3.6
are reserved modes, so please do not set any of them.
Table 3.6
Clock Operating Modes
Signal
Crystal
SCK3–SCK0
EXTAL/Crystal
Mode
MD2
MD1
MD0
PLL
Osc.
DIV1
at Reset
Frequency (MHz)
0
000
*
1
Off
1000
1–20*
2
1
001
*
1
On
Off
1000
2–20*
2
010
*
1
Off
0000
1–30*
2
3
011
*
1
Off
On
0000
2–30*
3
4
1
0
On
Off
0000
8–15
5
1
0
1
On
Off
0000
8–15
Notes: 1. PLL is on if the PLLO bit of FRQMR is 1; otherwise PLL is off.
2. Frequency range for when PLL is off. If PLL is on, frequency is limited to 8–15 MHz.
3. Frequency range for when PLL is off. If PLL is on, frequency is limited to 16–30 MHz.