- 您现在的位置：买卖IC网 > PDF目录16067 > IPR-POSPHY4 (Altera)IP POS-PHY L4 RENEW PDF资料下载
参数资料
| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 103/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页当前第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
Chapter 6: Testbench
Receiver Testbench Examples
There are three pattern generation functions capable of generating idles, training
patterns, and data packets. Table 6–2 shows the format of each function.
Table 6–2. Function Format
6–3
Command
Training
pattern
Idle
Data packet
Format
spi_gen.tp (width, number)
spi_gen.idles (number)
spi_gen.pkt (port_number,
err, size, num)
Description
width is the number of clock cycles the training pattern takes;
number is the number of training pattern sequences.
number is the number of sequential idles
port_number is the target port for the packet. err is set to zero;
size is the packet size in bytes (2-2 16 bytes); num is the packet
sequence number.
All of the packets are sent in sequence with no breaks between them. However, idles
can be inserted by adding the idle command in the testbench data generation section.
After all packets have been sent, the idle pattern is repeated until the end of the
simulation.
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the Atlantic packet receivers (data analyzer modules, one for
each port) have not detected any errors in the received packets. If no errors have been
detected, and all packets have been received, the testbench issues a message stating
that the simulation is successful.
If errors have been detected, a message states that the testbench has failed. If not all
packets have been detected, a message states that the testbench is incomplete. The
tb.exp_chk_cnt variable determines the number of checks done to ensure
completeness of the testbench. For each port tested, one completeness check is done.
In addition, a final check is done for the conclusion of the testbench.
Optionally, the testbench can create backpressure on the SPI-4.2 interface. When the
backpressure variable is defined, backpressure is generated on one or more ports by
first turning off the data analyzer receiver for the appropriate port. As the receive
FIFO buffer begins to fill, it goes from the hungry state to the satisfied state. When the
FIFO buffer is satisfied, the status on the SPI-4.2 interface notifies the packet
generation module to stop sending data. There is a break in packet generation during
which idles are sent. After the status returns to the hungry state, the packet generation
resumes.
Receiver Testbench Examples
In addition to the tasks described in Table 6–2 on page 6–3 , the packet generation
module also has the following four tasks, which you can use to generate error signals
when running the testbench:
■
■
■
■
pkt2
task_cw
task_cw2
task_pay
Table 6–3 describes the four error generation tasks in more detail.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| MAX6337US20D3+T | IC MPU/RESET CIRC 2.00V SOT143-4 |
| M3CWK-3436R | IDC CABLE - MKC34K/MC34M/MPL34K |
| M3AWK-3436R | IDC CABLE - MSC34K/MC34M/MPL34K |
| M3CKK-3436R | IDC CABLE - MKC34K/MC34M/MPK34K |
| M3AKK-3436R | IDC CABLE - MSC34K/MC34M/MPK34K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。