参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 54/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
4–14
Chapter 4: Functional Description—Receiver
Error Flagging and Handling
SPI-4.2 Protocol Errors
The receiver MegaCore function decodes the control words from the incoming SPI-4.2
interface and ensures that they follow the state machine shown in Fig. 6.2. Data Path
State Diagram of the SPI-4.2 Specification , and ensures that there are no other errors.
Table 4–3 summarizes the SPI-4.2 protocol errors.
Table 4–3. SPI-4.2 Protocol Error Handling (Part 1 of 3) (Note 1) , (2)
Error
Condition
Response
A transition on the receiver data path that does not follow
■
Assert err_rd_pr for one clock
Protocol error
Fig. 6.2. Data Path State Diagram of the SPI-4.2
Specification.
cycle.
Start-of-packet spacing
violation (SOP8)
Start of burst error
(SOB)
The SPI-4.2 specification states that SOP control words
should not be less than 8 cycles apart.
Data or training data is received without a payload control
word.
■
■
■
Asserts err_rd_sop8 for one
clock cycle. When this happens,
the data is not affected.
Assert err_rd_sob for one
cycle.
Data is dropped until a proper
payload control word is received.
Training pattern errors ( err_rd_tp ) occur when one of the
following conditions occur:
■
Assert err_rd_tp at the end of
the training pattern.
■
■
Training control portion is too short.
Training control portion is too long.
■
■
Channel aligner may not lock.
Some training pattern errors may
Training pattern error
■
■
■
Training data portion is too short.
Training data portion is too long.
Training control word is followed by something other
result in successive assertions of
the err_rd_tp interrupt (for
example, Training Control portion
> 10 cycles).
than another training control word or training data
word.
■
■
Malformed data bus during a data or control word.
Missing IDLE before training pattern begins. (The IDLE
can be an EOP).
■
■
Assert err_rd_eightn for one
clock cycle.
Packet is marked as errored.
8N boundary error
(8N_ERR)
A burst that is neither a multiple of 16 bytes, nor an EOP.
■
■
Consider error as a missing EOP.
Cleanly terminate packet
internally as an EOP-Abort. (3)
POS-PHY Level 4 MegaCore Function User Guide
■
Process subsequent bursts as
per missing SOP.
May 2013 Altera Corporation
相关PDF资料
PDF描述
MAX6337US20D3+T IC MPU/RESET CIRC 2.00V SOT143-4
M3CWK-3436R IDC CABLE - MKC34K/MC34M/MPL34K
M3AWK-3436R IDC CABLE - MSC34K/MC34M/MPL34K
M3CKK-3436R IDC CABLE - MKC34K/MC34M/MPK34K
M3AKK-3436R IDC CABLE - MSC34K/MC34M/MPK34K
相关代理商/技术参数
参数描述
IPR-QDRII/UNI 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RAPIDIOII 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RIOPHY 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDII/UNI 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDRAMII 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors