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| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 49/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description—Receiver
Block Description
4–9
1
Due to the round trip latency of the status channel, especially at high calendar
lengths, the hysteresis between the AE and AF values (in addition to the possibility of
the override capabilities listed above) may be such that a transition from starving to
satisfied (and vice versa) can occur. In the event that a transmitting device does not
allow these types of transitions (require hungry state to be observed between starving
and satisfied), you should ensure that the difference between AE and AF values is
greater than the hysteresis between the thresholds.
Figure 4–3. Receiver External Status Timing Diagram
rxsys_clk
ctl_ry_extstat
2'b00
2'b00
2'b00
2'b00
2'b01
2'bxx
2'bxx
2'bxx
2'b01
2'b00
2'b10
ctl_ry_extstat_val
ctl_ry_extstat_adr
8'd0
8'd0
8'd0
8'd1
8'd1
8'd0
8'd0
8'd0
8'd2
8'd3
8'd1
(1) The external status address does not have to be incrementing. Any value within calendar length can be provided at any time.
(2) The calendar status after the last clock cycle shown has: port 0 = 2’b00 , port 1 = 2’b10 , port 2 = 2’b01 , and port 3 = 2’b00 .
The external status address you provide does not have to be incrementing or have any
set sequence. You can provide any address value, at any time. If the external address
provided is for an unprovisioned port, the value is written into the internal RAM at
that address, but the internal status block never reads from that location.
The status hold block reads the contents of the memory where you have stored the
status of the external FIFO buffer(s).
The status calculator block compares the Atlantic FIFO buffer fill levels to the AE and
AF values for the requested port. In the shared buffer with embedded addressing
mode, because there is a single Atlantic FIFO buffer, the status for any port is
calculated according to the single level as opposed to a per-port basis.
The outgoing status of all ports is forced to satisfied ,if the datapath clock-crossing
buffer or Atlantic buffer overflows.
The FIFO buffer status of each port is encoded in 2 bits (refer to Table 4–1 ) and is
transmitted synchronous to the rsclk .
Table 4–1. Status Channel Field Descriptions (Part 1 of 2)
MSB
1
1
0
LSB
1
0
1
Description
Reserved for framing
SATISFIED—FIFO buffer is almost full. No new credits should be granted in the far
end scheduler.
HUNGRY—FIFO buffer is at a midpoint. MaxBurst2 credits should be granted in the
far end scheduler.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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相关代理商/技术参数 |
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| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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