参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 90/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
5–18
Table 5–5. Atlantic Transmit Interface (Slave Sink)
(Note 1)
Chapter 5: Functional Description—Transmitter
Signals
Signal
Direction
Clock
Domain
Description
Atlantic Clock (one for each Atlantic interface). This input is absent
aN_atxclk
aN_atxdav
aN_atxena
aN_atxdat[?:0]
Input
Output
Input
Input
and internally connected to tdint_clk if a single clock domain is
selected. Signals prefixed with aN_ are synchronous to this clock.
Atlantic data available (one for each Atlantic interface). Asserted when
the Atlantic FIFO buffer has at least ctl_atx_fth bytes of free space
available.
Atlantic enable (one for each Atlantic interface).
Atlantic data bus (one for each Atlantic interface). The width is set by
the Atlantic interface width parameter.
aN_atxsop
aN_atxeop
Input
Input
aN_atxclk
Atlantic start of packet (one for each Atlantic interface).
Atlantic end of packet (one for each Atlantic interface).
Atlantic empty signal (one for each Atlantic interface). Number of
aN_atxmty[?:0]
aN_atxerr
aN_atxadr[7:0]
Input
Input
Input
invalid octets on the lower bits of aN_atxdat . Valid only when
aN_atxeop is asserted, must be zero otherwise. The width is
log2(Atlantic interface width/8) .
Atlantic Error (one for each Atlantic interface). Translates to an EOP-
Abort on the transmit data bus.
Atlantic port address. Only present when you turn on turn on Shared
Buffer with Embedded Addressing .
Note to Table 5–5 :
(1) N is equal to the number of ports for the individual buffers mode; N is equal to zero when you turn on Shared Buffer with Embedded
Addressing .
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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