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| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 115/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
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Appendix A: Start-Up Sequence
A–5
Troubleshooting
data output, and the phase relation can be selected. There are notes on how to
do this in the top-level file. In either case the functional simulation models
need to be refreshed using the tool command language (Tcl) script provided.
for details.
■
This issue could be jitter related. Try adjusting the bandwidth of the PLLs. In
the fast PLLs, embedded in the ALTLVDS megafunction, this is done by adding
a pll_bandwidth_type parameter to the ALTLVDS instance. This parameter
can be low , medium , high , and defaults to auto , which should be high . The
following code is a Verilog HDL code example:
altlvds_rx_component.pll_bandwidth_type = "low"
■
Ensure the LVDS input pins have differential termination resistors. Some
devices do not contain internal termination resistors (check the device
datasheet), so you must place the 100 ohm resistors externally. For Altera
development kits, ensure you mount the termination resistors on the board.
6. Receiver (particularly third-party receivers) detects protocol errors related to burst
length. The following tips may prove useful:
■
■
If the transmitter is an embedded address variation, ensure that bursts are
written into the FIFO buffer in multiples of ctl_td_burstlen, or eop
terminated.
Ensure that ctl_td_burstlen is less than the buffer size.
7. Throughput is lower than expected. The following tips may prove useful:
■
■
■
■
■
■
Understand quantization effects and choose transmitter mode (lite or non-lite),
data path width, and clock frequencies appropriate for your packet size and
throughput needs.
Ensure all clocks are operating at their specified frequencies.
Ensure transmitter queue(s) always has data, otherwise factor into expectation.
Ensure receiver queue(s) always has space, otherwise factor into expectation.
Ensure status is sent or received as expected, which includes checking
stat_ts_sync , stat_td_holb , ctl_ts_status_mode , ctl_ry_fifostatoverride ,
ctl_ry_ae and ctl_ty_af .
Ensure credits ( ctl_td_mb1 and ctl_td_mb2 ) are large enough that they do not
run out between status updates.
Issues and Tips—Miscellaneous
Miscellaneous unexpected behavior:
■
■
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Ensure all clocks are up and operating at their specified frequencies.
Ensure all resets have been asserted, and released only after clock stabilization.
Ensure all signals connected to the MegaCore function are driven or sampled with
the appropriate clock.
Ensure all parameters are set as specified.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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