参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 91/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
Chapter 5: Functional Description—Transmitter
Signals
Table 5–6. Atlantic Buffer Control and Status
5–19
Signal
ctl_ax_fth[?:0]
ctl_ax_errchk_chkpkt
err_td_fifo_parityN
Direction Clock Domain
Input -
Static
reset
Input -
Static
reset
Output
Description
FIFO buffer threshold high determines when to
inform the user logic that space is available via the
aN_atxdav signals. Units are in bytes. Value applies
to all Atlantic buffers. Only change at reset.
Atlantic buffer error checking enable. Disable to
bypass missing SOP and missing EOP detection and
correction. Value applies to all Atlantic buffer levels.
Only change at reset.
Indicates that the FIFO buffer has detected a parity
error (one for each Atlantic buffer).
Indicates that the FIFO buffer has underflowed.
stat_td_fifo_emptyN
Output
aN_atxclk
Asserted for one cycle if a buffer read fails because
the buffer is empty (one for each Atlantic interface).
err_aN_fifo_oflwN
err_aN_msopN
err_aN_meopN
stat_aN_mp_erradrN[7:0]
Output
Output
Output
Output
Indicates that the FIFO buffer has overflowed, and
data has been lost (one for each Atlantic interface).
Indicates a missing start of packet error was detected
on the incoming Atlantic interface.
Indicates a missing end of packet error was detected
on the incoming Atlantic interface.
Address qualifier for err_aN_meopN and
err_aN_msopN flags. ( Shared Buffer with
Embedded Addressing only.)
.
Table 5–7. SPI-4.2 Status Channel Control and Status (Part 1 of 3)
Signal
Direction
Clock Domain
Description
Controls the filtering of framed status. Set to one to
select optimistic processing of status, otherwise set
to zero for pessimistic processing of status.
ctl_ts_status_mode
Input -
Static reset
tsclk
Pessimistic behavior only passes status from the last
calendar multiplier in error free frames to the user
and scheduler. Optimistic behavior has the least
latency, passing all status to the user and scheduler
before determining if the status frame is error free.
Only change at reset.
stat_ty_extstat_val
Output
Valid qualifier for the received status value, after
optimistic/pessimistic filtering.
stat_ty_exstat_adr[7:0]
stat_ty_exstat[1:0]
May 2013
Altera Corporation
Output
Output
txsys_clk
Port number for the received status value.
Received status value.
POS-PHY Level 4 MegaCore Function User Guide
相关PDF资料
PDF描述
MAX6337US20D3+T IC MPU/RESET CIRC 2.00V SOT143-4
M3CWK-3436R IDC CABLE - MKC34K/MC34M/MPL34K
M3AWK-3436R IDC CABLE - MSC34K/MC34M/MPL34K
M3CKK-3436R IDC CABLE - MKC34K/MC34M/MPK34K
M3AKK-3436R IDC CABLE - MSC34K/MC34M/MPK34K
相关代理商/技术参数
参数描述
IPR-QDRII/UNI 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RAPIDIOII 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RIOPHY 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDII/UNI 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDRAMII 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors