- 您现在的位置：买卖IC网 > PDF目录16067 > IPR-POSPHY4 (Altera)IP POS-PHY L4 RENEW PDF资料下载
参数资料
| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 30/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
3–8
1
Chapter 3: Parameter Settings
Optional Features
If you turn on Ignore backpressure (only available when you turn on Shared buffer
with embedded addressing ), the MegaCore function ignores the backpressure from
the receiver and simply sends data whenever the buffer is not empty. The MegaCore
function stops reading from the buffer only when the status framer is out of
synchronization, when a training pattern is inserted, or when there is not enough data
to complete a burst. The user logic is responsible for using the status outputs from the
MegaCore function to schedule data writes into the buffer appropriately.
If you turn off Ignore backpressure , a simple scheduling algorithm is employed. If
the status received for any port is satisfied, the transmitter stops reading from the
buffer on the next EOP or burst unit size boundary. If all ports are hungry or starving,
the transmitter sends the data in the buffer. So a satisfied status received for one port
prevents transmission for any port, leading to head-of-line blocking.
If you turn on Switch on end-of-packet , the scheduler stops sending from the current
port, and switches ports at the end of burst (that is, when the credits have all been
consumed), as well as when an EOP is sent. If you turn off Switch on end-of-packet ,
the scheduler switches ports at the end of the burst (also includes switching when the
buffer is empty).
This option applies only to the individual buffers mode, and allows you to
parameterize the port switching capabilities of the transmit scheduler.
Turn on Burst Limit Enable , if you want the transmitter to limit the maximum size of
bursts it sends. Set the maximum burst value with the Burst Limit option (on the
Protocol Parameters tab). At the end of a burst limit a control word is inserted.
Receiver Options
If you turn off Ignore LVDS DPA locked after training , which is only available for
Stratix II devices, a loss of dpa_lvds_locked causes the MegaCore function to stop
processing data, sends framing, and there is data loss and the possibility of
MSOP/EOP errors. If you turn on Ignore LVDS DPA locked after training , a loss of
dpa_lvds_locked does not trigger stop and framing, and data continues to process
normally. You must monitor the DIP4 error signal to assess if the data is correct or not
and trigger a retrain or not.
1
For Stratix III and Stratix IV devices, the dpa_lvds_locked signal never goes low, so
the MegaCore function behaves as if you turned on Ignore LVDS DPA locked after
training .
If the signal stat_rd_lvds_lock goes low during operation (after training), the
MegaCore function assumes that the lock is lost due to external conditions such as
jitter. This signal goes low if the capture phase of the hardware DPA block changes by
two or more phases. The two phases correspond to a amount that is lower than the
accepted threshold for the SPI4.2 Specification . When the signal goes low, the
MegaCore function states it is out of synchronization and requests a new training
sequence.
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| MAX6337US20D3+T | IC MPU/RESET CIRC 2.00V SOT143-4 |
| M3CWK-3436R | IDC CABLE - MKC34K/MC34M/MPL34K |
| M3AWK-3436R | IDC CABLE - MSC34K/MC34M/MPL34K |
| M3CKK-3436R | IDC CABLE - MKC34K/MC34M/MPK34K |
| M3AKK-3436R | IDC CABLE - MSC34K/MC34M/MPK34K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。